• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.233-236
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• 2005

Our country compares with advanced nations by supply of super high speed network and information communication infra construction has gone well very. Many people by extension of on-line transaction and various internet services can exchange, or get information easily in this environment. But, virus or poisonous information used to Cyber terror such as hacking was included within such a lot of information and such poisonous information are threatening national security as well as individual's private life. There were always security and speed among a lot of items to consider networks equipment from these circumstance to now when develop and install in trade-off relation. In this paper, we present a high speed VPN Acceleration Board(VPN-AB) that balances both speed and security requirements of high speed network environment. Our VPN-AB supports two VPN protocols, IPsec and SSL. The protocols have a many cryptographic algorithms, DES, 3DES, AES, MD5, and SHA-1, etc.. The acceleration board process data packets into the system with In-line mode. So it is possible that VPN-AB processes inbound and outbound packets by 10Gbps. We use Nitrox-II CN2560 security processor VPN-AB is designed using that supports many hardware security modules and two SPI-4.2 interfaces to design VPN-AB.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.2
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• pp.241-251
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• 2015

In public-key cryptographic system based on finite field arithmetic, it is very important to challenge for implementing high speed operation. In this paper, we focused on 8-bit ATmega128 processor and concentrated on enhancing efficiency of reduction operation which uses irreducible polynomial $f(x)=x^{271}+x^{207}+x^{175}+x^{111}+1$ and $f(x)=x^{193}+x^{145}+x^{129}+x^{113}+1$. We propose optimized reduction algorithms which are designed to reduce repeated memory accesses by calculating final reduced values of Fast reduction. There are 53%, 55% improvement when proposed algorithm is implemented using assembly language, compare to previous Fast reduction algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1491-1500
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• 2001

본 논문에서는 AES Rijndael 암호 알고리즘을 구현하는 암호 프로세서를 설계하였다. 하드웨어 공유를 통해 면적을 감소시키기 위해 1라운드 동작을 2개의 부분 라운드로 나누고 각 부분 라운드를 4 클록으로 구현하였다. 라운드 당 평균 5 클록의 연산 효율을 만들기 위해 인접한 라운드간에 부분 라운드 라이프라인 동작 기법을 적용하고, 키 설정 오버헤드 시간을 배제하기 위해, 암호 및 복호 동작의 라운드 키를 온라인 계산 기법을 사용하여 생성하였다. 그리고 다양한 응용 분야에 적용하기 위해, 128, 192, 256 비트의 3가지 암호 키를 모두 지원할 수 있도록 하였다. 설계된 암호 프로세서는 약 36,000개의 게이트로 구성되며 0.25$\mu\textrm{m}$ CMOS 공정에서 약 200Mhz의 동작 주파수를 가지며, 키 길이가 128 비트인 AES-128 ECB 동작 모드에서 약 512 Mbps의 암.복호 율의 성능을 얻을 수 있었다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.951-954
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• 2002

This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-1, HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-1 module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.345-348
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• 2000

본 논문에서는 현재 우리나라 전자상거래 표준인 SEED 암호화 알고리즘을 하드웨어로 구현하였다. 이 암호화 프로세서는 유연성과 하드웨어 면적을 줄이기 위해 파이프라인이 없는 1 unrolled loop 구조를 사용하였다. 그리고 ECB, CBC, CFB, OFB의 4가지 모드를 모두 지원할 수 있도록 하였다. key computation은 오버헤드를 감소시키도록 precomputation 기법을 사용하였다. 또한, 데이타 입ㆍ출력 시 증가되는 처리시간을 제거하기 위하여 외부 입ㆍ출력 레지스터와 data 입ㆍ출력 레지스터를 분리하여 데이타 입ㆍ출력 연산이 암호 프로세서의 암호화 연산과 병행하여 처리되도록 하였다. 암호 프로세서는 0.25$\mu\textrm{m}$ CMOS 기술을 사용하여 검증하였고 gate수는 대략 29.3K gate 정도가 소요되었으며, 100 MHz ECB 모드에서 최고 237 Mbps의 성능을 보였다.

• The KIPS Transactions:PartC
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• v.11C no.4
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• pp.439-446
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• 2004

In the Internet, user authentication is the most important service in secure communications. Although password-based mechanism is the most widely used method of the user authentication in the network, people are used to choose easy-to-remember passwords, and thus suffers from some Innate weaknesses. Therefore, using a memorable password it vulnerable to the dictionary attacks. The techniques used to prevent dictionary attacks bring about a heavy computational workload. In this paper, we describe a recent solution, the Optimal Strong-Password Authentication (OSPA) protocol, and that it is vulnerable to the stolen-verifier attack and an impersonation attack. Then, we propose an Improved Optimal Strong-Password Authentication (I-OSPA) protocol, which is secure against stolen-verifier attack and impersonation attack. Also, since the cryptographic operations are computed by the processor in the smart card, the proposed I-OSPA needs relatively low computational workload and communicational workload for user.

• Journal of Internet Computing and Services
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• v.21 no.3
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• pp.11-19
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• 2020

In this paper, a merged TEA block cipher processor which unifies Tiny Encryption Algorithm(TEA), extended Tiny Encryption Algorithm(XTEA) and corrected block TEA(XXTEA) is designed. After TEA cipher algorithm was first designed, XTEA and XXTEA cipher algorithms were designed to correct security weakness. Three types of cipher algorithm uses a 128-bit master key. The designed cipher processor can encrypt or decrypt 64-bit message block for TEA/XTEA and variable-length message blocks up to 256-bit for XXTEA. The maximum throughput for 64-bit message blocks is 137Mbps and that of 256-bit message blocks is 369Mbps. The merged TEA block cipher designed in this paper has a 16% gain on the area side compared to a lightweight LEA cipher. The cryptographic IP of this paper is applicable in security module of the mobile areas such as smart card, internet banking, and e-commerce.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.183-191
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• 2023

Cryptographic algorithms require extensive computational resources and rely on complex mathematical principles for security. However, IoT devices have limited resources, leading to insufficient computing power. As a result, lightweight cryptography has emerged, which uses fewer computational resources. NIST organized a competition to standardize lightweight cryptography and TinyJAMBU, one of the algorithms in the competition, is a permutation-based algorithm that repeats many permutation operations. In this paper, we implement TinyJAMBU on an 8-bit AVR processor with a proposedtechnique that includes a reverse shift method and precomputing some operations in a fixed key and nonce environment. Our techniques showed a maximum performance improvement of 7.03 times in permutation operations and 5.87 times in the TinyJAMBU algorithm, improving up to 9.19 times in a fixed key and nonce environment.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.5
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• pp.1017-1026
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• 2012

Due to acceleration of the IT industry and the environment for a variety of media in modern society, such as real-time video images 3D-TV is a very important issue. These high-quality live video is being applied to various fields such as CCTV footage has become an important performance parameters. However, these high quality images, even vulnerable because of shortcomings secure channel or by using various security algorithms attempt to get rid of these disadvantages are underway very active. These shortcomings, this study added extra security technologies to reduce the processing speed image processing itself, but by adding security features to transmit real-time processing and security measures for improving the present.