• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• International Journal of Computer Science & Network Security
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• v.21 no.8
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• pp.17-27
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• 2021

Non-abelian group based cryptosystems are a latest research inspiration, since they offer better security due to their non-abelian properties. In this paper, we propose a novel approach to non-abelian group based public-key cryptographic protocols using semidirect products of finite groups. An intractable problem of determining automorphisms and generating elements of a group is introduced as the underlying mathematical problem for the suggested protocols. Then, we show that the difficult problem of determining paths and cycles of Cayley graphs including Hamiltonian paths and cycles could be reduced to this intractable problem. The applicability of Hamiltonian paths, and in fact any random path in Cayley graphs in the above cryptographic schemes and an application of the same concept to two previous cryptographic protocols based on a Generalized Discrete Logarithm Problem is discussed. Moreover, an alternative method of improving the security is also presented.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.959-960
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• 2008

Recently, biometric authentication mechanism has been used to provide high level of security in cryptographic systems. In this paper, we propose an efficient method of generating invariant iris key to be applied in cryptographic systems. In order to generate iris key and improve the performance at the stolen token scenario, multiple random projection technique was combined with multiple linear transformation methods. From the experimental results, we proved that invariant iris keys were generated and the proposed method was robust to stolen token scenario.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.3-10
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• 2007

In this paper, we show that the status certificate-based encryption(SCBE) scheme proposed at ICISC 2004 and the certificateless signature(CLS) scheme proposed at EUC workshops 2006 are insecure. Both schemes are claimed that an adversary has no advantage if it controls only one of two participants making a cryptographic key such as a decryption key in SCBE or a signing key in CLS. But we will show that an adversary considered in the security model of each scheme can generate a valid cryptographic key by replacing the public key of a user.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.339-341
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• 2023

This paper presents a multithread and efficient cryptographic hardware access (MECHA) for efficient and fast cryptographic operations that eliminates the need for context switching. Utilizing a UNIX domain socket, MECHA manages multiple requests from multiple applications simultaneously, resulting in faster processing and improved efficiency. We comprise several key components, including the Server thread, Client thread, Transceiver thread, and a pair of Sender and Receiver queues. MECHA design is portable and can be used with any communication protocol, with experimental results demonstrating a 83% increase in the speed of concurrent cryptographic requests compared to conventional interface design. MECHA architecture has significant potential in the field of secure communication applications ranging from cloud computing to the IoT, offering a faster and more efficient solution for managing multiple cryptographic operation requests concurrently.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.177-182
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• 1998

This paper proposes pure master key which can be commonly used in multi-cryptographic system. It also refer to master key condition for RSA public key cryptosystem using Format's theorem and master key algorithm as well.

• The KIPS Transactions:PartC
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• v.17C no.1
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• pp.47-60
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• 2010

Randomness is a basic security evaluation item for the most cryptographic algorithms. NIST has proposed a statistical test suit for random number generators for cryptographic applications in the process of AES project. However the test suit of NIST is customized to block ciphers which have the same input and output lengths. It needs to revise NIST's test suit for key derivation functions which have multiple output blocks. In this paper we propose a revised method of NIST's statistical randomness test adequate to the most key derivation functions and some experimental results for key derivation functions of 3GSM and NIST.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.136-139
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• 2000

In this paper, we propose a prime code and a new cryptographic algorithm for encryption and decryption as its application. The characteristics of prime numbers with irregular distribution and uniqueness are used to generate the prime code. Based on the prime code, an encryption algorithm for secret key is presented. Since the algorithm requires simpler operations than existing encryption such as DES, the burden for hardware implementation of the encryption and decryption process is alleviated.