• Journal of Institute of Control, Robotics and Systems
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• v.14 no.4
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.11
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• pp.1794-1798
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• 2004

We present a fabrication method of high aspect ratio 100nm-scale nickel stamper using e-beam writing for the injection molding of optical grating patterns. Conventional nickel stamper is fabricated by nickel electroplating process which is followed by seed layer deposition. In this paper, we have used chrome coated blank mask without anti-reflection layer of CrON in order to simplified electroplating process. In experimental study, we have optimized electron-beam dosage for 100nm-scale optical grating patterns with 2.5-aspect ratio, and fabricated nickel stamper using above grating patterns as PR mold. Fabricated nickel stamper have showed height of 240$\pm$20nm and width of 116$\pm$6nm.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.339-339
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• 2002

In the RABiTS approach to coated conductor development, successful (both economic and technological) depends on the refinement and optimization of each of three important components: the metal tape substrate, the buffer layer(s), and the HTS layer. Here we will report on the ORNL approach and progress in each of these areas. - Most applications will require metal tapes with low magnetic hysteresis, mechanical strength, and excellent crystalline texture. Some of these requirements are competing. We report on progress in obtaining a good combination of these characteristics on metal alloys of Ni-Cr and Ni-W. - The deposition of appropriate buffer layers is a crucial step. Recently, base research has shown that the presence of a stable sulfur superstructure present on the metal surface is needed for the nucleation and epitaxial growth of vapor-deposited seed buffer layers such as YSZ, CeO$_2$ and SrTiO$_3$. We report on the details and control of this superstructure for nickel tapes, as well as recent results for Cu and Ni-13%Cr. - Processes for deposition of the HTS coating must economically provide large values of the figure-of-merit for conductors, current x length. At ORNL, we have devoted efforts to a precursor/post-annealing approach to YBCO coatings, for which the deposition and reaction steps are separate. We describe motivation for and progress toward developing this approach. - Finally, we address some issues for the implementation of coated conductors in real applications, including the need for texture control and electrical stabilization of the HTS coating.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.33-33
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• 2007

SoP-L 공정은 유전율이 상이한 재료를 이용하여 PCB 공정이 가능하고 다른 packaging 방법에 비해 공정 시간과 비용이 절약되는 잠정이 있다. 본 연구에서는 SoP-L 기술을 이용하여 Si 기판의 함몰에 판한 공정의 안정도와 함몰 시 제작된 때턴의 특성의 변화에 대해 관찰 하였다. Si 기판의 함몰에 Active device를 이용하여 특성의 변화를 살펴보고 공정의 안정도를 확립하려 했지만 Active device는 측정 시 bias의 확보와 특성의 민감한 변화로 인해 비교적 측정이 용이하고 공정의 test 지표를 삼기 위해 passive device 를 구현하여 함몰해 보았다. Passive device 의 제작 과정은 Si 기판 위에 spin coating을 통해 PI(Poly Imide)를 10um로 적층한 후에 Cr과 Au를 seed layer로 증착을 하였다. 그리고 photo lithography 공정을 통하여 photo resister patterning 후에 전해 Cu 도금을 거쳐 CPW 구조로 $50{\Omega}$ line 과 inductor를 형성하였다. 제작 된 passive device의 함몰 전 특성 추출 data와 SoP-L공정을 통한 함몰 후 추출 data 비교를 통해 특성의 변화와 공정의 안정도를 확립하였다. 차후 안정된 SoP-L 공정을 이용하여 Active device를 함몰 한다면 특성의 변화 없이 size 룰 줄이는 효과와 외부 자극에 신뢰도가 강한 기판이 제작 될 것으로 예상된다.