• Title/Summary/Keyword: Coupling Capacitance

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Design of Inductive coupled wideband LC Balun Embedded Into Organic Substrate (유기기판에 내장된 인덕터의 커플링을 이용한 광대역 LC 발룬의 설계)

  • Park, Jong-C.;Park, Jae-Y.
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.1502-1503
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    • 2007
  • In this paper, inductive coupled LC balun has been desi gned and simulated for embedding into an organic packaging substrate. Inductive coupling method was applied to obtain wide band characteristics, and high dielectric film was utilized to reduce a size of the balun. The proposed balun has a novel scheme which consists of three embedded LC resonators with inductive coupling. This proposed balun has relatively small inductance and capacitance values which can be easily embedded into the organic packaging substrate. Furthermore, it has a good phase imbalance characteristic. The simulated results of proposed balun are an insertion loss of 1.2 dB, a return loss of 10 dB, a phase imbalance of 1 degree at frequency bandwidth of 750 MHz ranged from 1.8 GHz to 2.55 GHz, respectively. This balun has an area of $2mm{\tims}3.5mm{\times}0.66mm$ (height).

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Balance Winding Scheme to Reduce Common-Mode Noise in Flyback Transformers

  • Fu, Kaining;Chen, Wei
    • Journal of Power Electronics
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    • v.19 no.1
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    • pp.296-306
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    • 2019
  • The flyback topology is being widely used in power adapters. The coupling capacitance between primary and secondary windings of a flyback transformer is the main path for common-mode (CM) noise conduction. A Y-cap is usually used to effectively suppress EMI noise. However, this results in problems in space, cost, and the danger of safety leakage current. In this paper, the CM noise behaviors due to the electric field coupling of the transformer windings in a flyback adapter with synchronous rectification are analyzed. Then a scheme with balance winding is proposed to reduce the CM noise with a transformer winding design that eliminates the Y-cap. The planar transformer has advantages in terms of its low profile, good heat dissipation and good stray parameter consistency. Based on the proposed scheme, with the help of a full-wave simulation tool, the key parameter influences of the transformer PCB winding design on CM noise are further analyzed. Finally, a PCB transformer for an 18W adapter is designed and tested to verify the effectiveness of the balance winding scheme.

Analysis of Transmission-line Discontinuities by 3-dimensional Finite Element Method (3차원 유한요소법에 의한 도파로의 불연속 특성 해석)

  • 이상수;안창회;정봉식;이수영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.5
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    • pp.355-360
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    • 1991
  • A transmission-line discontinuities are analyzed by Finite Element Method. We use quasi-static approxmation to determine the circuit parameters of discontinuities. Delta formulation is introduced so that the cancellation error of potential calculation is reduced. To verify this method, capacitance of coaxial cable with discontinuous and coupling capacitances are calculated by modal expansion. This approach can be used for arbitrary discontinuous conducting patterns of microwave devices.

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The Research on Vertical Block Mura in TFT-LCD

  • Long, Chunping;Wang, Wei;Wu, Hongjiang
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.841-844
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    • 2007
  • In this paper, a vertical block mura, which massively occurred in the LCD products, was investigated extensively by various methods, source drain (SD) line shift is found out to be one of the key reasons. This work to some extent, establishes theoretic hypothesis for further research and solutions similar issues.

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Electrical properties of multilayer piezoelectric actuator with the variations of temperature (적층 압전액츄억이터 소자의 온도해 따른 전기적 특성)

  • Lee, Kab-Soo;Lee, Il-Ha;Yoo, Ju-Hyun
    • Proceedings of the KIEE Conference
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    • 2006.10a
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    • pp.63-64
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    • 2006
  • In this paper, multilayer piezoelectric actuator was fabricated in order to develop ultrasonic linear motor. Multilayer actuator showed a high density of 7.78[$g/cm^3$], a large effective electromechanical coupling factor($K_{eff}$) of 0.259, a high mechanical quality factor( Qm ') of 1301, and high capacitance(c) of 19.32[nF]. Curie temperature was $343[^{\circ}C]$.

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Design and Analysis of 2 GHz Low Noise Amplifier Layout in 0.13um RF CMOS

  • Lee, Miyoung
    • Journal of Advanced Information Technology and Convergence
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    • v.10 no.1
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    • pp.37-43
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    • 2020
  • This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (Cex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.

Clamped capacitance control of a piezoelectric single crystal vibrator using a generalized impedance converter circuit (범용 임피던스 변환회로를 이용한 압전 단결정 진동자의 제동용량 제어)

  • Kim, Jungsoon;Kim, Moojoon
    • The Journal of the Acoustical Society of Korea
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    • v.37 no.1
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    • pp.46-52
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    • 2018
  • The piezoelectric single crystals used in piezoelectric transformers have a problem that power transfer capacity is comparatively low due to their high input impedance. In this study, we suggest a method to improve the power transfer capacity by reducing the high input impedance of the piezoelectric single crystal vibrator by connecting a capacitance increasing circuit to the electrical terminals of the piezoelectric single crystal vibrator where the circuit is a GIC (Generalized Impedance Converter) circuit using operational amplifiers. The result of measuring driving characteristics after applying the designed capacitance increasing circuit to the $128^{\circ}$ rotated Y-cut $LiNbO_3$ crystal vibrator confirmed that the input impedance decreased by 25 %, electromechanical coupling factor increased by 30 %, and the power transfer capacity increased by about 17 to 30 times in voltage conversion characteristics.

Test Generation for Multiple Line Affecting Crosstalk Effect (다중 전송선에 영향을 받는 Crosstalk 잡음을 위한 테스트 생성)

  • Lee, Young-Gyun;Yang, Sun-Woong;Kim, Moon-Joon;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.9
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    • pp.28-36
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    • 2002
  • As cross-coupling capacitance generated in transmission line has been an important issue in VLSI world, a couple of ATPG algorithms has been proposed. However they were studied only for a simple single-line effect problem, so it cost so much time for an unsatisfying test generation efficiency. In this paper, we studied a noise model for multiple affected lines and generated test patterns in a short time. This paper proposes a crosstalk model affected by multiple tranmission lines and implemented an ATPG algorithm for detection of crosstalk noise faults. We modeled the crosstalk noise by multiple transmission line and made a truth table for this. We implemented an ATPG algorithm based on PODEM and revealed the results.

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

  • Lee, Jung-Hwan;Jeon, Seong-Do;Chang, Sung-Keun
    • ETRI Journal
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    • v.26 no.6
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    • pp.583-588
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    • 2004
  • In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

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Design of an SIR BPF by a Novel EM Tuning of Individual Resonators (개별 공진기의 EM 조정을 통한 SIR로 구성된 대역 여파기의 설계)

  • Yang, Seong-Sik;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.7
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    • pp.748-756
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    • 2007
  • In SIR filter, fringing capacitances and discontinuities yield a distorted frequency response from those expected by design formulas, especially in higher frequencies. In this paper, a procedure is presented in order to compensate for fringing capacitances and step impedance discontinuities by EM simulation for a 5th order SIR filter. This method propose the procedure of tuning the coupling and the length of individual resonator by EM simulation. For the filter composed by the tuned resonators, no further tuning is required. The procedure is experimentally justified by comparing the measured data of the fabricated filter with the simulation results.