• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.52-58
• /
• 2013

Replacement policy is one of the key factors determining the effectiveness of a cache. The LRU replacement policy has remained the standard for caches for many years. However, the traditional LRU has ineffective performance in zero-reuse line intensive workloads, although it performs well in high temporal locality workloads. To address this problem, We propose a new replacement policy; DCR(Dynamic Counter based Replacement) policy. A temporal locality of workload dynamically changes across time and DCR policy is based on the detection of these changing. DCR policy improves cache miss rate over a traditional LRU policy, by as much as 2.7% at maximum and 0.47% at average.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.1016-1021
• /
• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.41-49
• /
• 2008

This paper presents a design of the control block of a passive UHF RFID tag IC according to EPCglobal Class-1 Generation-2 UHF RFID 1.1.0 Protocol. The control block includes a PIE block, CRC5/CRC16, a Slot Counter, a Random Number Generator, a Main Control Block, a Encoder and a Memory Interface. The control block has been designed using the Verilog HDL and has been simulated. Functional simulation results for the overall control block operation show that 11 instructions with 7 states are operated correctly. Also, the control block has been implemented with 36,230 gates by Synopsys Design Compiler and Apollo using Magnachip 0.25$\mu$m technology.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.5
• /
• pp.32-38
• /
• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• The Korean Journal of Archival Studies
• /
• no.53
• /
• pp.45-77
• /
• 2017

This study intends to rehabilitate the memories of the social other which have been gradually forgotten in the social events overloaded with the undemocratic violence in South Korea today. This study explores a case of Yongsan Tragedy in 2009 among the most tragic events. It notes the autonomous ways in which activist artists would like to memorize the socio-historical events anew despite the emptiness of public records. In other words, this study considers the Yongsan case to be significant that a group of the public, artists, grassroots activists, religion men got together in solidarity so as to create the contested narratives countering dominant memories and thus to signify the records written by the civil society. Among others, activist artists had documented the unofficial counter-memories of socially alienated peoples in terms of planning a series of artistic events such as opening some gallery exhibitions and performance events, issuing a volume of work books, comics and photographies, online broadcasting, and directing some documentaries. Especially, this paper tends to note the documentation of on-site activist artists to record the counter-memories against social oblivion. By doing so, it finally suggests how we could document the Yongsan Tragedy both to search out the archival implications of today's art activism and to insert those artistic records into the commonly shared counter-memories in a more inclusive way.

• Journal of Korea Multimedia Society
• /
• v.18 no.11
• /
• pp.1367-1374
• /
• 2015

In this paper, we propose a model which can prioritize the performance improvement work by analyzing the major risks and their influence, which can cause performance degradation in the system and show an example of a performance improvement using this model. In presentation-tier, as a result of log data analysis before and after the performance improvement of key processes which handle financial transactions, this model brought the CPU utilization and memory enhancement in the performance improvement work of the financial system which was carried out by applying the proposed model. It has been confirmed that the entire end-user can be accommodated. In the web-tier, the available memory increased by 200MB and we were able to improve the server restart(Recycling) that was sustained in the existing system. In the business logic-tier, we have been able to see better figures after performance improvements through the graph which analyzes the log collected with the key performance counters such as CPU%, Batch Requests/sec. In the data-tier, it has been confirmed that CPU usage and standby operation were reduced and the throughput was found to increase.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.1
• /
• pp.167-180
• /
• 1996

In the scalar processing oriented machine scalar operations must be performed for the vector processing as many as the number of vector components. So called a vector processing mechanism by the von Neumann operational principle. Accessing vector data hasto beperformed by theevery pointing ofthe instruction or by the address calculation of the ALU, because there is only a program counter(PC) for the sequential counting of the instructions as a memory accessing device. It should be here proposed that an access unit dimensionally to address components has to be designed for the compensation of the organizational hardware defect of the conventional concept. The necessity for the vector structuring has to be implemented in the instruction set and be performed in the mid of the accessing data memory overlapped externally to the data processing unit at the same time.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.57 no.2
• /
• pp.135-139
• /
• 2008

MFISFETs with platinum electrode on the $LiNbO_3$/aluminum nitride/Si(100) structures were successfully fabricated and the properties of the FETs have been discussed. $I_D-V_G$ characteristics of MFISFETs for linear region (that is, 0.1 V of the drain voltage) showed hysteresis loop with a counter-clockwise trace due to the ferroelectric nature of $LiNbO_3$ films. A memory window (i.e., threshold voltage shift) of the fabricated device was about 2[V] for a sweep from -4 to +4[V]. The estimated field-effect electron mobility and transconductance on a linear region were 530[$cm^2/V{\cdot}s$] and 0.16[mS/mm], respectively. The drain current of 27[${\mu}A$] on the "on" state was more than 3 orders of magnitude larger than that of 30[nA] on the "off" state at the same "read" gate voltage of l.5[V], which means the memory operation of the MFISFET.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.181-189
• /
• 2001

In this thesis, a policing algorithm is proposed, which is one of the traffic management function in ATM networks. The proposed algorithm minimizes CLR(Cell Loss patio) of high priority cells and solves burstiness problem of the traffic caused by multiplexing and demultiplexing process. The proposed algorithm has been implemented with VHDL and is divided into three parts, which are an input module, an UPC module, and an output module. In implementation of the UPC module\`s memory access, memory address is assigned according to VCI\`s LSB(Lowest Significant Byte) of ATM header for convenience. And the error of VSA operation from counter\`s wrap-around can be recovered by the proposed method. ANAM library 0.25 $\mu\textrm{m}$ and design compiler of Synopsys are used for synthesis of the algorithm and Synopsys VSS tool is used for VHDL simulation of it

• Proceedings of the KSRS Conference
• /
• 2003.11a
• /
• pp.1096-1098
• /
• 2003

SBC(Single Board Computer) is being developed for MSC(Multi-Spectral Camera) on KOMPSAT-2(Korea Multi-Purpose Satellite). SBC controls all the units of MSC system and gets commands and sends telemetry to and from spacecraft bus via 1553 communication channel. Due to the fact that SBC does very important roles for MSC system operation and SBC operates with 100% duty cycle, SBC is designed to have high reliability. SBC which has Intel 80486 as a main processor includes eight serial communication channels, one mil-std-1553 interface channel and several discrete interfaces. SBC incorporates 2Mbyte radiation hardened SRAM(Static Random Access Memory) and 1Mbyte flash memory. There are also PIC(Programmable Interrupt Controller), counter, WDT(Watch Dog Timer) in the SBC. In this paper, the design result of the SBC is presented.