• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.11
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• pp.2127-2130
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• 2008

In this paper, a tunable bandpass filter with mutual inductive coupling circuits is newly designed and demonstrated for UHF TV tuner ranged from Ch.14(473MHz) to Ch.69(803MHz) applications. Conventional HF tuning circuit with an electromagnetic bandpass filter has several problems such as large size, high volume and high cost, since the electromagnetic filter is comprised of several passive components and air core inductors to be assembled and controlled manually. To address these obstacles, peaking chip inductor was newly applied for constructing the mutual inductive coupling circuit. The proposed circuit was newly and optimally designed, since the chip inductor showed lower components Q-value than the air core inductor. A varactor diode has been also used to fabricate the proposed tunable bandpass filter for RF tuning circuit. The fabricated tunable filter exhibited low insertion loss of approximately -3dB, high return loss of below -10dB, and large tuning bandwidth of 330MHz.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.3
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• pp.261-265
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• 2012

In this study, glassy carbon was ground for lens core of glass mold press. Ultraprecision grinding process was applied for machining of core surfaces. During the process, brittle crack occurred because of hard-brittleness of glassy carbon. Author investigated optimized grinding conditions from the viewpoint of ductile mode grinding. Geometrical undeformed chip thickness was adopted for critical chip thickness that enables crack free surface. Machined cores are utilized for biaspheric glass lens fabrication and surfaces of lens were compared for verification of ground surface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.8
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• pp.780-784
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• 2006

We present high aspect ratio air-core solenoid inductors with $100{\mu}m\;and\;200{\mu}m$ tall via structures on Pyrex wafer. The effect of various parameters such as different number of turns, via heights, pitch distance between turns on inductor's radio frequency (RF) characteristics have been studied. The highest Q factor we obtained from various solenoid inductors is 72.8 at 9.7 GHz, which was produced by a 3-turn inductor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• Animal cells and systems
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• v.14 no.1
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• pp.1-10
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• 2010

Previously we showed that CHIP, a co-chaperone of Hsp70 and E3 ubiquitin ligase, can promote the degradation of mutant SOD1 linked to familial amyotrophic lateral sclerosis (fALS) via a mechanism not involving SOD1 ubiquitylation. Here we present evidence that CHIP functions in the interaction of mutant SOD1 with 26S proteasomes. Bag-1, a coupling factor between molecular chaperones and the proteasomes, formed a complex with SOD1 in an hsp70-dependent manner but had no direct effect on the degradation of mutant SOD1. Instead, Bag-1 stimulated interaction between CHIP and the proteasome-associated protein VCP (p97), which do not associate normally. Over-expressed CHIP interfered with the association between mutant SOD1 and VCP. Conversely, the binding of CHIP to mutant SOD1 was inhibited by VCP, implying that the chaperone complex and proteolytic machinery are competing for the common substrates. Finally we observed that mutant SOD1 strongly associated with the 19S complex of proteasomes and CHIP over-expression specifically reduced the interaction between S6/S6' ATPase subunits and mutant SOD1. These results suggest that CHIP, together with ubiquitin-binding proteins such as Bag-1 and VCP, promotes the degradation of mutant SOD1 by facilitating its translocation from ATPase subunits of 19S complex to the 20S core particle.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.161-172
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• 1994

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.