• Journal of Power Electronics
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• v.14 no.2
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• pp.217-225
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• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.493-500
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• 2015

A flyback converter operates with either pulse width modulation (PWM) or pulse frequency modulation (PFM) control scheme depending on the load current. At light load condition, PFM control is employed to reduce the switching frequency and thereby minimize the switching power loss. For heavier load, PWM control is used to regulate the output voltage of the flyback converter. The flyback controller has been implemented in a $0.35{\mu}m$ BCDMOS process and applied to a 40-W flyback converter. The light-load power efficiency of the flyback converter is improved up to 5.7-% comparing with the one operating with a fixed switching frequency.

• Journal of Power System Engineering
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• v.6 no.3
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• pp.64-70
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• 2002

A fast decoupled algorithm for time domain simulation of power electronics circuits is presented. The circuits can be arbitrarily configured and can incorporate feedback amplifier circuits. This simulation algorithm is performed for the input series output parallel connected 2 switch forward converter. Steady state and large signal transient responses due to a step load change are simulated. The simulation results are verified through experiments.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.7
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• pp.384-390
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• 1999

This paper describes a new ac-to-dc power converter using a multilevel converter. A conventional multilevel ac-to-dc converter has large output dc filter capacitors. When a short circuit happens in a load, the stored energy in the capacitors should be discharged through the load with a high short circuit current. The high current may cause considerable damage to the capacitors and the load. The output dc capacitors of the proposed converter do not discharge even under load short circuit condition. In the case of a load short circuit, the capacitors become a floating state immediately and remain in the state. Then the stored capacitor energy is supplied to the load again as soon as the short circuit has been cleared. Therefore, the rising time of the load voltage can be significantly reduced. This feature satisfies the requirement of a power supply for a load with frequent short circuits. The proposed converter has the characteristics of a simplified structure, a reduced cost, weight, and volume compared with conventional power supplies with frequent output short circuits. Experimental results are presented to verify the usefulness of the proposed converter.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.74-78
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• 1998

The shortcomings of zero-voltage-transition PWM converter is discussed and a new family of topologies of zero-voltage-transition PWM converter with soft-switched auxiliary switch is introduced. The experiments on a 290W boost converter and a 100W forward converter are carried out to prove the circuit. The efficiency increment of the new circuits are 2-5% comparing to hard switching circuits, and the switching noise is also greatly reduced.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Journal of Power Electronics
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• v.11 no.1
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• pp.1-9
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• 2011

This paper describes a two quadrant bidirectional soft switching converter for ultra capacitor interface circuits. The total efficiency of the energy storage system in terms of size and cost can be increased by a combination of batteries and ultra capacitors. The required system energy is provided by a battery, while an ultra capacitor is used at high load power pulses. The ultra capacitor voltage changes during charge and discharge modes, therefore an interface circuit is required between the ultra capacitor and the battery. This interface circuit must have good efficiency while providing bidirectional power conversion to capture energy from regenerative braking, downhill driving and the protecting ultra capacitor from immediate discharge. In this paper a fully soft switched two quadrant bidirectional soft switching converter for ultra capacitor interface circuits is introduced and the elements of the converter are reduced considerably. In this paper, zero voltage transient (ZVT) and zero current transient (ZCT) techniques are applied to increase efficiency. The proposed converter acts as a ZCT Buck to charge the ultra capacitor. On the other hand, it acts as a ZVT Boost to discharge the ultra capacitor. A laboratory prototype converter is designed and realized for hybrid vehicle applications. The experimental results presented confirm the theoretical and simulation results.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.8
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• pp.517-524
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• 2004

In this paper, a novel zero-voltage-switching(ZVS) resonant DC-DC converter is proposed. It is composed of two symmetrical active-clamped circuits, the converter can be achieve ZVS in each switches. Also, active clamp capacitor ratios($\alpha$) of proposed circuit can be reduce a peak stress of switching voltage for each main switch. Simulation results using Pspice 9.2 ver and $C^{++}$ characteristic analysis show a provement for the validity of theoretical analysis. The analysis of the proposed Current-Fed Push Pull type DC-DC converter is generally described by using normalized parameter, and achieved an evaluated characteristic values which is needed to design a circuit. We confirm a rightfulness theoretical analysis by comparing a theoretical values and experimental values obtained from experiment using MOSFET as switching devices.

• Journal of Power Electronics
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• v.4 no.4
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• pp.197-204
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• 2004

Two-stage Power-Factor-Correction (PFC) converters are the most common circuits for drawing sinusoidal and in phase current waveforms from an ac source with a good regulated output voltage. The first stage is a boost PFC converter with average-current-mode control for achieving the near-unity power factor and the second stage is a forward converter with voltage-mode control to regulate the output voltage. Stability analysis and design methods of two-stage PFC converters have previously been discussed using linear models. Recently, new nonlinear phenomena have been detected in pre-regulator boost PFC circuits and a new nonlinear model has been proposed for pre-regulated PFC converters. Therefore, investigation of two-stage PFC converters from the nonlinear viewpoint becomes important because the second stage DC/DC converter adds more complexity to the circuit. So, this paper introduces a study of the stability of two-stage PFC converters. A novel nonlinear model of two-stage PFC converters is proposed. Then, a stability analysis is made based upon this nonlinear model. The high correspondence between the simulated and experimental results confirms our analysis.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.212-216
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• 2001

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitic capacitance between the drain/collector of an active switch and the frame ground through its heat sink may generate the common-mode conducted noise. We have proposed a balanced switching converter circuit, which is an effective way to reduce the common-mode conducted noise. As an example, a boost converter version of the balanced switching converter was presented and the mechanism of the common-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switching converter circuit and presents a buck-boost converter version of the balanced switching converter. The feature of common-mode noise reduction is confirmed by experimental results and the mechanism of the common-mode noise reduction is explained using equivalent circuits.