• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.419-421
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• 1996

We propose the digitized pressure sensor and the interface circuit to read directly the pressure signal in the digital form. The interface circuit has the control clock, comparator, and bit value decision circuit. The digitized sensor and interface circuit are integrated on the one chip using the post processing after IC fabrication. The dimension of the fabricated digitized pressure sensor is $3{\times}6{\times}1mm^3$.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.980-985
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• 1988

In this paper, a control system of the PUMA 560 robot manipulator using a PC (Personal Computer) is presented. The hardware of the designed control system is composed of IBM-PC/AT, interface board, selection board, interrupt generating circuit, and the servo control unit of the PUMA controller. A robot control library is developed using assembly and C language, and is composed of several low-level functions and arm interface routines, world model routines, arm kinematics routines, and motion command service routines. Using the designed library, joint interpolated motion and Cartesian interpolated motion of the PUMA robot manipulator are realized. In the future, our system is expected to be a very helpful basis and a useful tool for developing various control algorithms of robot manipulator using sensory information.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• Journal of the Korea Computer Graphics Society
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• v.2 no.2
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• pp.53-60
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• 1996

In 3D graphics interface, 3D objects and virtual camera have many degrees of freedom. We interpret the control of 3D objects and virtual camera as a problem of kinematics and inverse kinematics. It is well known that extra degrees of freedom introduce various singularities in inverse kinematics. In this paper, we approach 3D graphics interface problems by reducing redundant degrees of freedom so that the control degrees of freedom matches with the degrees of freedom in the motions of 3D objects and virtual camera.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 2002.10a
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• pp.285-288
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• 2002

For real-time flood forecasting and effective control flood at the Youngsan estuary dam, the Flood Forecasting and Control User Interface System II (FFCUS II) has been developed. This paper describes the features and application of FFCUS II. FFCUS II is composed of the database management subsystem, the model subsystem, and the graphic user interface. The database management subsyem collects rainfall data and stream flow data, updates, processes, and searches the data. The model subsystem predicts the inflow hydrograph, the tide, forecasts flood hydrograph, and simulates the release rate from the sluice gates. The graphic user interface subsystem aids the user's decision-making process by displaying the operation results of the database management subsystem and model subsystem.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.7
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• pp.592-598
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• 2013

In this paper, a small, lightweight smartphone-controlled riding robot is developed. Also, in this study, a smartphone with a jog shuttle mode for consideration of user convenience is proposed to make a small, lightweight riding robot. As well, a compass sensor is used to compensate for the mechanical characteristics of motors mounted on the riding robot. The riding robot is controlled by the interface of a drag-based jog shuttle in the smartphone, instead of a mechanical controller. For a personal riding robot, if the smartphone is used as a controller instead of a handle or a pole, it reduces its size, weight, and cost to a great extent. Thus, the riding robot can be used in indoor spaces such as offices for moving or a train or bus station and an airport for scouting, or hospital for disabilities. Experimental results show that the riding robot is easily and conveniently controlled by the proposed smartphone interface based on Android.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.107-110
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• 2001

Recently, there are lots of concerning on robot agent system working for itself with the trends of the research of bio-mimetic system and intelligent robot. In this paper, a virtual 3D interface system is proposed based on Internet for remote controlling and monitoring of mobile robot. The proposed system is constructed as manager-agent model. A worker can order the robot agent move to a new position by clicking the destination on virtual space of 3D graphic interface in manager. Then the robot agent move to the position automatically with avoiding collision by using range finding and autonomous control algorithm. The proposed robot agent system lets us control the mobile robot remotely located more conveniently.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2003.10a
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• pp.11-15
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• 2003

In order to suppress a repulsive interfacial energy between hydrophilic clay and hydrophobic polymer matrix in preparing a polymer/clay nanocomposite, a third component of amphiphilic nature such as poly($\varepsilon$-caprolactone) (PCL) was introduced into the model system of styrene-acrylonitrile copolymers (SAN)/Na-montmorillonite. Once $\varepsilon$-caprolactone was polymerized in the presence of Na-rnontmorillonite, the successful ring-opening polymerization of $\varepsilon$-caprolactone and the well-developed exfoliated structure of PCL/Na-montmorillonite mixture were confirmed, Thereafter, SAN was melt-mixed with PCL/Na-montmorillonite nanocomposite, which resulted in that SAN matrix and PCL fraction were completely miscible to form homogeneous mixture with retention of the exfoliated state of Na-montmorillonite, exhibiting that PCL effectively stabilizes the repulsive polymer/clay interface and contributes the improvement of mechanical properties of the nanocomposites.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1129-1132
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• 1999

This paper deals with the design and implementation of an Ethernet-based communication protocol to be used in PC-based I/O interface systems. Recently, the performance of PC systems is being highly improved and Ethernet is used as the stable communication network over the world. We develop a new protocol driver with the capability of accessing Ethernet directly using NDIS(Network Driver Interface Specification), the network interface standard of Windows O.S. in PC, and install it at the application layer of the protocol structure. Its major roles are the supplement of CSMA/CD algorithm, the effective use of the long data frame of Ethernet, and the real-time transmission of data frames. This paper represents the possibility of the real-time control network and systems based on PCs and Ethernet.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.