• Bulletin of the Korean Mathematical Society
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• v.43 no.1
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• pp.119-123
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• 2006

Let G be a symmetric group. In this paper we describe a method that for a certain irreducible character X of G it finds a subgroup H such that the restriction of X on H has a linear constituent with multiplicity one. Then using a well known algorithm we can construct a representation of G affording X.

• International Journal of Computer Science & Network Security
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• v.21 no.4
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• pp.33-40
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• 2021

The traveling salesman problem (TSP) is one of the well-known and extensively studied NPC problems in combinatorial optimization. To solve it effectively and efficiently, various optimization algorithms have been developed by scientists and researchers. However, most optimization algorithms are designed based on the concept of improving route in the iterative improvement process so that the optimal solution can be finally found. In contrast, there have been relatively few algorithms to find the optimal solution using route construction mechanism. In this paper, we propose a route construction optimization algorithm to solve the symmetric TSP with the help of ratio value. The proposed algorithm starts with a set of sub-routes consisting of three cities, and then each good sub-route is enhanced step by step on both ends until feasible routes are formed. Before each subsequent expansion, a ratio value is adopted such that the good routes are retained. The experiments are conducted on a collection of benchmark symmetric TSP datasets to evaluate the algorithm. The experimental results demonstrate that the proposed algorithm produces the best-known optimal results in some cases, and performs better than some other route construction optimization algorithms in many symmetric TSP datasets.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.85-93
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• 1984

In the paper, a new constructive initial placement algorithm is proposed in computer aided layout design in LSI. An useful object function are proposed to place the modules in logic design diagram laid down by manual to the fixed chip, reflecting the relative positions between modules and cells, and then an initial placement are determined by the function. In order to show the usefulness of the proposed method, it was compared with clustering development method in maximum cut numbers and total routing lengths by program experiments.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.37-42
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• 2009

The performance of an OLED(organic luminescent emitting device) fabrication system strongly depends on the design of the evaporation cell-source. Trends in display sizes have hauled the enlargement of mother glass substrates. The enlargement of substrates requires the improvement and the enlargement of the effusion cell-source for OLED evaporation process. The deposited layers should be as uniform as possible, and therefore it is important to know the effusion profile of the molecules emitted from the cell-source. Conventional 2D DSMC algorithm cannot be used for simulating the new concept cell-source design, such as a linear source. This work concerns the development of 3D DSMC (direct simulation Monte Carlo) analysis for simulating the behavior of the evaporation cell-sources. In this paper, the 3D DSMC algorithm was developed and the film thickness profiles were obtained by the numerical analysis.

• Journal of Computing Science and Engineering
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• v.4 no.3
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• pp.240-252
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• 2010

One of the important open problems in modeling plants is the extension of subdivision algorithms to branching structures. Most of the applications use the concept of L-system to produce branching structures as a sequence of lines and apply the subdivision scheme to appear as curves. In this paper, we explain how L-systems can be modified to produce branching structures. This is also very useful for generating the geometry of various shapes. The proposed technique, called an adaptive L-System, describes branching forms and leaves by making local curve without applying the subdivision steps. Advantages of the suggested algorithm over previous techniques are given. Validation of the algorithm are discussed, analyzed and illustrated by some experimental results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.16-23
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• 1998

In this paper, we present a fast and efficient Iterative Improvement Partitioning(IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. The IIP algorithms are very widely used in VLSI circuit partition due to their time efficiency. As the performance of these algorithms depends on choices of moving cell, various methods have been proposed. Specially, Cluster-Removal algorithm by S. Dutt significantly improved partition quality. We indicate the weakness of previous algorithms wjere they used a uniform method for choice of cells during for choice of cells during the improvement. To solve the problem, we propose a new IIP technique that selects the method for choice of cells according to the improvement status and present hybrid bucket structures for easy implementation. The time complexity of proposed algorithm is the same with FM method and the experimental results on ACM/SIGDA benchmark circuits show improvment up to 33-44%, 45%-50% and 10-12% in cutsize over FM, LA-3 and CLIP respectively. Also with less CUP tiem, it outperforms Paraboli and MELO represented constructive-partition methods by about 12% and 24%, respectively.

• Journal of the Korean Society of Systems Engineering
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• v.8 no.1
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• pp.1-7
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• 2012

This research aims to propose a model to estimate the appropriate SE Cost rate to the total project cost when systems engineering applied to light rail transit project. In this research an investment cost estimation model is proposed with reference to COSYSMO (Constructive System Engineering Cost Model). This model includes four input factors such as requirement numbers, interface numbers, algorithm numbers, and scenario numbers. When 2600 requirement numbers are considered on a proposal document with 350 pages in a light rail transit specification of 500 billion~trillion won scale, COSYSMO demo version estimates 42.5 billion won of SE cost (about 5% of total project cost or about 10% of E&M cost).

• Structural Engineering and Mechanics
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• v.22 no.6
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• pp.685-700
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• 2006

The effective length factor is a familiar concept for practicing engineers and has long been an approach for column stability evaluations. Neglecting the effects of axial force in the restraining members, in the case of sway prevented frames, is one of the simplifying assumptions which the Alignment Charts, the conventional nomographs for K-Factor determination, are based on. A survey on the problem reveals that the K-Factor of the columns may be significantly affected when the differences in axial forces are taken into account. In this paper a new iterative approach, with high convergence rate, based on the general principles of structural mechanics is developed and the patterns for detection of the critical member are presented and discussed in details. Such facilities are not available in the previously presented methods. A constructive methodology is outlined and the usefulness of the proposed algorithm is illustrated by numerical examples.

• Transactions on Control, Automation and Systems Engineering
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• v.2 no.4
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• pp.248-254
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• 2000

This paper presents and output feedback fuzzy H(sup)$\infty$ control problem for a class of nonlinear systems with time-varying delayed state. The Takagi-Sugeno fuzzy model is employed to represent a nonlinear systems with time-varying delayed state. Using a single quadratic Lyapunov function, the globally exponential stability and disturance attenuation of the closed-loop fuzzy control system are discussed. Sufficient conditions for the existence of fuzzy H(sup)$\infty$ controllers are given in terms of matrix inequalities. Constructive algorithm for design of fuzzy H(sup)$\infty$ controller is also developed. A simulation example is given to illustrate the performance of the proposed design method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.49-57
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• 1993

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.