• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1401-1411
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• 1999

Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.248-250
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• 2005

This paper suggests a new type of 4-switch inverter for switched reluctance motor drives. 4-switch Inverter topology is studied to provide possibility for the realization of cost of 3-phase SRM drive system. We used Y-connection and two-phase exciting method. For effective utilization of the developed system, a direct current controlled PWM scheme is designed and implemented to produce the desired dynamic. We solve to balance the neutral point of Y-connection by the direct current controlled PWM and examine the performance of proposed system. With the algorithm and developed control scheme, is expected that the proposed system can be widely used in commercial applications with a reduced system cost.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.27-33
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• 2003

This paper proposes the efficient audit method for the distributed connection information in ATM switch. Based on this method, we design the periodic audit function by a system and immediate audit function by a operator's order. We evaluate the performance about the proposed Audit method. At the result of evaluation, We figure out that the load of call control processor is almost independent of a system load regardless of audit function operation. Therefore, we confirm that the proposed audit method nearly have an effect on the load of call control processor. The proposed audit method can reestablish a Mismatched connection information with a little load.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.4
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• pp.341-352
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• 1990

In this paper, we introduce tree types of switching networks, I, e., a fully segregated type, a partially integrated type, and a fully integrated type switch, to accommodate nx 64Kb/s multi-slot connection traffic and analyze their blocking probabilites for the different traffic mixes by utilizing a computational algorithm of blocking probability, and finally determine the traffic handling capacity which satisfies the given grade of service. The fully integrated type switch can accommodate the ISDN traffic with relatively low wideband traffic. However, either the partially integrated type or the fully segregated type switch is needed to accommodate the ISDN traffic as the wideband traffic increases. This result can be usilized in the design of ISDN switching networks accommodating multi-slot connection traffic.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.286-295
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• 2015

Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.

• The KIPS Transactions:PartC
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• v.12C no.3 s.99
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• pp.449-456
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• 2005

Optical burst switching (OBS) overcomes the inefficient resource usage of optical circuit switching and minimizes the optical buffering requirement of optical packet switching. General switch management protocol (GSMP) is an open interface between a label switch and a controller, and it provides connection, configuration, performance, event management and synchronization. GSMP open interface in the OBS network allows the implementation of OBS switch to be simple by separating the data forward plane from the control plane. We defined managed objects to support connection, configuration, performance, and fault management for the management of OBS network in the GSMP open interface. We proposed the network management model, in which the above managed objects are distributed in a controller and an OBS switch according to network management functions. We verified the possibility of connection management using distributed network management model in the GSMP open interface of OBS network by implementing GSMP and network management functions with managed objects of OBS.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.1-8
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• 1997

A wide class of networking application services, such as video teleconferencing, VOD, LAN bridging, and distributed data processing require multipoint communications. The essential component inteh network to achieve this is a multicast packet switch which is capable of packet replication and switching. In this paper, we propose an efficient mukticast addressing scheme using the smallest number of routing bits which is deterministic lower bound. The new scheme performs all point-to-multipoint connection in radix-2 tree ATM switch like banyan network. Also, we provide a simple radix-2 switch block diagram for achieving our algorithm. And we investigate several addressing schemes for implementing multicasting in radix-r tree ATM switch and evaluate several performance factors, such as complexity of the additional header bits, requirement of the internal speedup and complexity of the major hardware.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.109-116
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• 2016

This paper proposes an analytic model for four-switch inverter (FSI)-driven wye (Y) or delta (Δ)-connected motors with a current ripple reduction algorithm. FSIs employ four switches in controlling three-phase load instead of using six switches. They have split dc-link stage, and due to this inherent structure there exists the voltage difference between upper and lower capacitors, which results in distortion of the inverter output voltage. To study characteristics of FSIs, this paper presents an advanced simulation models of FSI-driven control system for 3-phase motor that can has a wire connection either Y or Δ. In addition, this paper introduces a current ripple reduction scheme that mitigates degradation of control performance due to the voltage difference between the dc-link capacitors. The validity of the proposed method and the analytic model is verified by simulations and experiments carried out with 1-HP induction machine with Y or Δ-connection

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1665-1674
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• 2000

This paper treats the interworking of LAN-based networks like TCP over the ATM protocol stack in an ATM multicast session. Multicast connection will cause CIP since multicast group members form a connection tree by some tree methods and share the connected tree. The paper solve the CIP problem through a block-by-block transmission using ABT/IT method. ABT/IT RM cell is modified and block scheduling algorithm considering the traffic types is applied to each ATM switch using the enhanced RM cell. Block scheduling algorithm will avoid the indiscriminate discard of UBR traffic when congestion occurs and it can provide an efficient and fair service. The paper builds a block scheduler system and suggests the block scheduling algorithm for a multicast session in an ATM switch. UBR traffics arriving at the switch trough each VC is classified by the traffic type and stored at class buffer and thereafter indisciminately transmitted. When block scheduling algorithm is applied it will improve the UBR traffic performance such as end-to-end delay cell block loss ration etc. This paper evaluated the performance of block scheduling algorithm through the simulation using the C language and data structure.