• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.936-939
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• 2002

FPCA is the necessary device to design of hardware at present, it is researched on many ways of applying to design caused by expansion of capacity in recent years. One of these applying ways is SoC (System on a Chip) that is proposed for realizing the basic function of a system. For realizing SoC efficiently, IP (Intellectual property) is very important and developed for re-use of hardware. A MPU for built-in exists as an IP. But almost of MPUs at present as an IPs are lengthy and large-scale for using embedded-application. Furthermore, the function of executing specific treatment critically is required to embedded MPU. We propose a flexible and small scale MPU and its design method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.1035-1037
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• 2009

Common to use fixed-node sensor network and wireless sensor networks, unlike the recent move of the node happens frequently. These wireless sensor networks by taking into account the mobility of sensor nodes dynamically self-configurable routing protocol is required. In this paper, a fixed-node configuration and energy efficiency in the self-LEACH protocol is based on the useful movement of the nodes of the cluster is dynamically self-configuring routing protocols offer M-LEACH.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.124-130
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• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.

• ETRI Journal
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• v.42 no.4
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• pp.534-548
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• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.7
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• pp.660-665
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• 2011

Reconfigurable Flight Simulator for an airborne tactical mission based on virtual reality technology is developed as a software configurable cockpit with computer display as virtual instruments. It can simulate F-15K, KF-16, T/A-50 class fighter and depending on simulated cockpit, control stick and throttle are replaceable. For effective immersion, Video See-Through type HMD is applied.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.192-200
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• 2018

In this study, improvements for error correction, speed, position, and rotation calculation algorithms have been proposed to be used in resolver to digital conversion (RDC) systems. The proposed open-loop system drives the resolver and uses the output signals of the resolver signal to estimate the real time position, the instant speed, and the rotation count with high resolution and accuracy even at high speeds and noise. The proposed solution implements strong features of both closed and open loop based systems while eliminating their weak points. The improvements proposed is resistant to noise owing to digital FIR filter and data averaging techniques. The implementation used for proof of concept is implemented on a hardware using an FPGA and configurable to be used by any resolver.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.52.4-52
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• 2001

In this paper we propose a framework of an open architectured manufacturing system base on CORBA middleware. The manufacturing system consists of four configurable software modules 9mchine control module, database module, monitoring module, and operation module). Each module is distributed through the network and integrated with CORBA middleware technology. CORBA Characteristics including independence from programming languages, computing platforms and networking protocols makes us to easily develop new applications and to effectively integrate new module into existing distributed systems. The CORBA program used in this study is The ACE ORB (TAO) developed by the laboratory in Washington University.

• Journal of the Optical Society of Korea
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• v.7 no.1
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• pp.28-33
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• 2003

We describe the optimal design and the fabrication of a 2$\times$2 port optical device based on the thin film filter (TFF), and also propose a 4-channel OADM module using these devices. The optical performance of the proposed OADM module is evaluated theoretically and experimentally, and is compared to that of typical OADM modules using 1$\times$2 port optical devices for 4, 8, 16 and 32 drop channels in optical transmission systems. Since the 2$\times$2 port optical device accomplishes the function of wavelength multiplexing and demultiplexing simultaneously in the proposed OADM module, the insertion loss of through channels can be improved by 1.2 dB compare to that of typical OADM modules using 1$\times$2 port optical devices. In addition, both the size and the price of the module can be reduced to 40~50%.