• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권11호
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• pp.3523-3543
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• 2022

Autonomous vehicles are gradually being regarded as the mainstream trend of future development of the automobile industry. Autonomous driving networks generate many intensive and delay-sensitive computing tasks. The storage space, computing power, and battery capacity of autonomous vehicle terminals cannot meet the resource requirements of the tasks. In this paper, we focus on the task scheduling problem of autonomous driving in software-defined edge networks. By analyzing the intensive and delay-sensitive computing tasks of autonomous vehicles, we propose an emotion model that is related to task urgency and changes with execution time and propose an optimal base station (BS) task scheduling (OBSTS) algorithm. Task sentiment is an important factor that changes with the length of time that computing tasks with different urgency levels remain in the queue. The algorithm uses task sentiment as a performance indicator to measure task scheduling. Experimental results show that the OBSTS algorithm can more effectively meet the intensive and delay-sensitive requirements of vehicle terminals for network resources and improve user service experience.

• 인터넷정보학회논문지
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• 제24권2호
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• pp.1-10
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• 2023

The Multi-access Edge Computing (MEC) paradigm equips network edge telecommunication infrastructure with cloud computing resources. It seeks to transform the edge into an IT services platform for hosting resource-intensive and delay-stringent services for mobile users, thereby significantly enhancing perceived service quality of experience. However, erratic user mobility impedes seamless service continuity as well as satisfying delay-stringent service requirements, especially as users roam farther away from the serving MEC resource, which deteriorates quality of experience. This work proposes a deep reinforcement learning based service mobility management approach for ensuring seamless migration of service instances along user mobility. The proposed approach focuses on the problem of selecting the optimal MEC resource to host services for high mobility users, thereby reducing service migration rejection rate and enhancing service availability. Efficacy of the proposed approach is confirmed through simulation experiments, where results show that on average, the proposed scheme reduces service delay by 8%, task computing time by 36%, and migration rejection rate by more than 90%, when comparing to a baseline scheme.

• International journal of advanced smart convergence
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• 제9권1호
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• pp.109-112
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• 2020

Many devices are connected on the internet to give functionalities for interconnected services. In 2020', The number of devices connected to the internet will be reached 5.8 billion. Moreover, many connected service provider such as Google and Amazon, suggests edge computing and mesh networks to cope with this situation which the many devices completely connected on their networks. This paper introduces the current state of the introduction of the wireless mesh network and edge cloud in order to efficiently manage a large number of nodes in the exploding Internet of Things (IoT) network and introduces the existing Network Time Protocol (NTP). On the basis of this, we propose a relatively accurate time synchronization method, especially in heterogeneous mesh networks. Using this NTP, multiple time coordinators can be placed in a mesh network to find the delay error using the average delay time and the delay time of the time coordinator. Therefore, accurate time can be synchronized when implementing IoT, remote metering, and real-time media streaming using IoT mesh network.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• 전자공학회논문지C
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• 제36C권8호
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• pp.1-9
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• 1999

빠르고 정확한 결과를 얻기 위해서 타이밍 수준에서의 회로 해석이 이루어지며, 게이트와 연결선에서의 신호 지연 해석은 회로의 설계 검증을 위하여 필수적이다. 본 논문에서는 CMOS 회로 게이트에서의 지연 시간과 연결선의 지연 해석을 위한 초기 천이 시간을 동시에 계산할 수 있는 방법을 제시한다. 회로 연결선의 유효 커패시턴스 개념을 이용하여 게이트의 지연 시간과 게이트에서의 구동 저항을 고려한 연결선 선형 전압원의 천이 시간을 계산한다. 게이트 지연과 연결선 선형 전압원의 천이 시간을 구하는 과정은 예비 특성화된 게이트 타이밍 데이터를 이용하여 반복적인 연산과정을 통하여 동시에 구하게 된다. 기존의 게이트 지연 계산 알고리즘은 연결선 선형 전압원의 천이 시간을 위해 별도의 게이트 특성 데이터를 필요로 하였으나, 본 논문에서 제시하는 방법은 계산 과정 중에 생성된 데이터를 이용함으로써 현재의 예비 특성화 방법을 수정하지 않고서도 효율적인 타이밍 수준의 게이트 및 연결선 지연 시간 예측이 가능하도록 하였다.

• 한국전자통신학회논문지
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• 제18권5호
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• pp.777-784
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• 2023

감지 증폭기는 메모리 설계에 필수적인 주변 회로로서, 작은 차동 입력 신호를 감지하여 디지털 신호로 증폭하기 위해 사용된다. 본 논문에서는 인 메모리 컴퓨팅 회로에서 활용 가능한 고속 감지 증폭기를 제안하였다. 제안하는 회로는 추가적인 방전 경로를 제공하는 트랜지스터 Mtail을 통해 감지 지연 시간을 감소시키고, m-GDI(:modified Gate Diffusion Input)를 적용하여 감지 증폭기의 회로 성능을 개선하였다. 기존 구조와 비교했을 때 감지 지연 시간은 16.82% 감소하였으며, PDP(: Power Delay Product)는 17.23%, EDP(: Energy Delay Product)은 31.1%가 감소하는 결과를 보였다. 제안하는 회로는 TSMC의 65nm CMOS 공정을 사용하여 구현하였으며 SPECTRE 시뮬레이션을 통해 본 연구의 타당성을 검증하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권4호
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• pp.1147-1161
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• 2023

The Internet of Things (IoT) requires a new processing model that will allow scalability in cloud computing while reducing time delay caused by data transmission within a network. Such a model can be achieved by using resources that are closer to the user, i.e., by relying on edge computing (EC). The amount of IoT data also grows with an increase in the number of IoT devices. However, building such a flexible model within a heterogeneous environment is difficult in terms of resources. Moreover, the increasing demand for IoT services necessitates shortening time delay and response time by achieving effective load balancing. IoT devices are expected to generate huge amounts of data within a short amount of time. They will be dynamically deployed, and IoT services will be provided to EC devices or cloud servers to minimize resource costs while meeting the latency and quality of service (QoS) constraints of IoT applications when IoT devices are at the endpoint. EC is an emerging solution to the data processing problem in IoT. In this study, we improve the load balancing process and distribute resources fairly to tasks, which, in turn, will improve QoS in cloud and reduce processing time, and consequently, response time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권11호
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• pp.5269-5286
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• 2018

Task scheduling is one of the key issues in improving system performance and optimizing resource management in cloud computing environment. In order to provide appropriate services for heterogeneous users, we propose a novel task scheduling strategy with service differentiation, in which the delay sensitive tasks are assigned to the rapid cloud with high-speed processing, whereas the fault sensitive tasks are assigned to the reliable cloud with service restoration. Considering that a user can receive service from either local SaaS (Software as a Service) servers or public IaaS (Infrastructure as a Service) cloud, we establish a hybrid queueing network based system model. With the assumption of Poisson arriving process, we analyze the system model in steady state. Moreover, we derive the performance measures in terms of average response time of the delay sensitive tasks and utilization of VMs (Virtual Machines) in reliable cloud. We provide experimental results to validate the proposed strategy and the system model. Furthermore, we investigate the Nash equilibrium behavior and the social optimization behavior of the delay sensitive tasks. Finally, we carry out an improved intelligent searching algorithm to obtain the optimal arrival rate of total tasks and present a pricing policy for the delay sensitive tasks.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권8호
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• pp.2764-2782
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• 2021

Existing city-level boundary nodes identification methods need to locate all IP addresses on the path to differentiate which IP is the boundary node. However, these methods are susceptible to time-delay, the accuracy of location information and other factors, and the resource consumption of locating all IPes is tremendous. To improve the recognition rate and reduce the locating cost, this paper proposes an algorithm for city-level boundary node identification based on bidirectional approaching. Different from the existing methods based on time-delay information and location results, the proposed algorithm uses topological analysis to construct a set of candidate boundary nodes and then identifies the boundary nodes. The proposed algorithm can identify the boundary of the target city network without high-precision location information and dramatically reduces resource consumption compared with the traditional algorithm. Meanwhile, it can label some errors in the existing IP address database. Based on 45,182,326 measurement results from Zhengzhou, Chengdu and Hangzhou in China and New York, Los Angeles and Dallas in the United States, the experimental results show that: The algorithm can accurately identify the city boundary nodes using only 20.33% location resources, and more than 80.29% of the boundary nodes can be mined with a precision of more than 70.73%.

• 한국전자통신학회논문지
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• 제18권2호
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• pp.291-298
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• 2023

SRAM 기반 인 메모리 컴퓨팅은 폰 노이만 구조의 병목 현상을 해결하는 기술 중 하나이다. SRAM 기반의 인 메모리 컴퓨팅을 구현하기 위해서는 효율적인 SRAM 비트 셀 설계가 필수적이다. 본 논문에서는 전력 소모를 감소시키고 회로 성능을 개선시키는 저 전력 차동 감지 8+T SRAM 비트 셀을 제안한다. 제안하는 8+T SRAM 비트 셀은 SRAM 읽기와 비트 연산을 동시에 수행하고 각 논리 연산을 병렬로 수행하는 리플 캐리 가산기에 적용한다. 제안하는 8+T SRAM 기반 리플 캐리 가산기는 기존 구조와 비교 하여 전력 소모는 11.53% 감소하였지만, 전파 지연 시간은 6.36% 증가하였다. 또한 이 가산기는 PDP(: Power Delay Product)가 5.90% 감소, EDP(: Energy Delay Product)가 0.08% 증가하였다. 제안한 회로는 TSMC 65nm CMOS 공정을 이용하여 설계하였으며, SPECTRE 시뮬레이션을 통해 타당성을 검증하였다.