• 한국전산유체공학회:학술대회논문집
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• 2005.04a
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• pp.35-40
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• 2005

Up to recently, with the improvement of a computer power and high speed of network technology, advanced countries have researched a construction of the e-Science environment. As a major application part, a construction for environment of CFD, also, have studied together. During the research, people realize that not sharing hardware but also appropriate software development is really important to realize the environment. This paper describes about a construction of a collaborative research environment in the KISTI: Clients can connect to the computing resources through the web portal, run the Cactus simulation.: According to the computing resources, the simulation can migrate to some site to find better computing power.: Result of the calculation visualize at the web portal directly so that researchers of remote site can be share and analyze the result collaborative ways.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06c
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• pp.74-76
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• 2011

최근 플래시 메모리에 기반을 둔 임베디드 시스템의 사용이 급증하고 있다. 스마트폰이 대중화됨에 따라, 플래시 메모리용 파일시스템에 대한 필요성이 증가되고 있다. 보편적으로 사용하는 YAFFS2 파일시스템은 초기화 시 오래 걸리는 단점이 존재하여 체크포인트 기능으로 보안 하고 있다. 그러나 갑작스러운 Power Failure 나 언마운트시 체크포인트가 저장되지 않으면 전체 영역을 스캔해야 하는 문제점이 존재한다. 본 논문에서는 YAFFS2의 성능 개선 및 신뢰성 향상을 위한 메타데이터 관리 기법을 제안한다. 메인메모리상에 유지되는 메타데이터의 영역을 나눠서 관리해서, Power Failure 가 발생하거나 체크포인트가 존재하지 않아도 전 영역을 스캔 하는 문제점 을 피할 수 있다.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.275-280
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• 2005

The principal context of this research is the approach to an artificial neural network algorithm which solves multivariable nonlinear equation systems by estimating the state of line power flow. First a dynamical neural network with feedback is used to find the minimum value of the objective function at each iteration of the state estimator algorithm. In second step a two-layer neural network structures is derived to implement all of the different matrix-vector products that arise in neural network state estimator analysis. For hardware requirements, as they relate to the total number of internal connections, the architecture developed here preserves in its structure the pronounced sparsity of power networks for which state the estimator analysis is to be carried out. A principal feature of the architecture is that the computing time overheads in solution are independent of the dimensions or structure of the equation system. It is here where the ultrahigh-speed of massively parallel computing in neural networks can offer major practical benefit.

• 전기의세계
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• v.23 no.1
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• pp.61-68
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• 1974

This paper attempts to develop the algorithms and computer program for load flow solution and faults analysis of large power system by small digital computer. The Conventional methods for load flow solution and fault analysis of large power system require too much amount of computer memory space and computing time. Therefore, this paper describes the methad for reducing the computer memory space and computing time as follows. (1) Load Flow Solution; This method is to store each primitive impedance of lines along with a list of bus numbers corresponding to the both terminals of lines, and to store only nonzero element of bus admittance matrix. (2) Faults Analysis: This method is to partition a large power system into several groups of subsystems, form individual bus impedance matrix, store them in the storage, and assemble the only required portion of them to original total system by algorithm.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.12
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• pp.435-440
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• 1983

The methods of forming the bus impedance matrix, which is mainly employed in fault analysis of power system, can be generally classified in catagories, (1) the one being the inverse matrix of bus admittance matrix, and (2) the other the bus impedance matrix succesive formation method by particular algorithms. The former method is theouetically elegant, but the formation and inverse of complex bus admittance matrix for large power system requires too much amounts of computer memory space and computing time. The latter method also requires too much memory space. Therefore, in this paper, an algorithm and computer program is introduced for the formation of a sparse bus impedance matrix which generates only the matching terms of the admittance matrix. So, this method can reduce the computer memory and computing time, and can be applied to fault analysis of large power system by small digital computer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1102-1108
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• 2020

Mobile edge computing is a technology that can prepare for a new era of cloud computing and compensate for shortcomings by processing data near the edge of the network where data is generated rather than centralized data processing. It is possible to realize a low-latency/high-speed computing service by locating computing power to the edge and analyzing data, rather than in a data center far from computing and processing data. In this article, we develop a virtual mobile edge computing testbed environment where the cloud and edge nodes divide computing tasks from mobile terminals using the EdgeCloudSim simulator. Performance of offloading techniques for distribution of computing tasks from mobile terminals between the central cloud and mobile edge computing nodes is evaluated and analyzed under the virtual mobile edge computing environment. By providing a virtual mobile edge computing environment and offloading capabilities, we intend to provide prior knowledge to industry engineers for building mobile edge computing nodes that collaborate with the cloud.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.61-64
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• 2003

Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. These sensors can be deeply embedded in the physical world and spread throughout sensor network environment like smart dust. So ubiquitous computing will be come true. SmartDust project is the one of ubiquitous computing approach. It produces TinyOS, mote(mica, mica2, rene2, mica2dot, etc.), NesC, TinyDB, etc. We constructs sensor network test bed and tests to approach sensor network and ubiquitous computing.

• Journal of applied mathematics & informatics
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• v.7 no.3
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• pp.1045-1058
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• 2000

In usual synchronous parallel computing, workload balance is a crucial factor to reduce idle times of some processors that have finished their jobs earlier than others. However, it is difficult to achieve on a heterogeneous workstation clusters where the available computing power of each processor is unpredictable. As a way to overcome such a problem, the idea of asynchronous methods has grown out and is being increasingly used and studied, but there is none for eigenvalue problems yet. In this paper, we suggest a new asynchronous method to solve some singular matrix problems, that can also be used for finding a certain eigenvector of some matrices.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.2
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• pp.444-461
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• 2016

A power-saving mechanism for smartphone devices is developed by analyzing the features of data that are received from Internet of Things (IoT) sensors devices to optimize the data processing policies. In the proposed GreenIoT architecture for power-saving in IoT, the power saving and feedback mechanism are implemented in the IoT middleware. When the GreenIoT application in the power-saving IoT architecture is launched, IoT devices collect the sensor data and send them to the middleware. After the scanning module in the IoT middleware has received the data, the data are analyzed by a feature evaluation module and a threshold analysis module. Based on the analytical results, the policy decision module processes the data in the device or in the cloud computing environment. The feedback mechanism then records the power consumed and, based on the history of these records, dynamically adjusts the threshold value to increase accuracy. Two smart living applications, a biomedical application and a smart building application, are proposed. Comparisons of data processed in the cloud computing environment show that the power-saving mechanism with IoT architecture reduces the power consumed by these applications by 24% and 9.2%.