• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.94-100
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• 1999

This paper concerns the implementation of a digital neural network which performs the high speed operation of Hopfield model's arithmetic operation. It is also designed to use a look-up table and produce floating point arithmetic of nonlinear function with high speed operation. The arithmetic processing of Hopfleld is able to describe the matrix-vector operation, which is adaptable to design the array processor because of its recursive and iterative operation .The proposed method is expected to be applied to the field of real neural networks because of the realization of the current VLSI techniques.

• International Journal of Computer Science & Network Security
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• v.22 no.11
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• pp.338-347
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• 2022

The current study aimed to identify the reality of the transitional services provided to people with intellectual disabilities from the parent's point of view. The results indicated an average level, with an arithmetic mean (3.66) of the reality of transitional services provided to students with intellectual disabilities through the response of the study participants to the questionnaire consisting of (20) items. The dimension (social and societal skills) ranked first with an arithmetic average (4.03) with a high degree, through the response of the participants in the study to the items of the dimension consisting of (10) items. It was followed by the dimension (self-determination skills) with an arithmetic average of (3.29) to a medium degree, through the response of the participants in the study to the items of the dimension consisting of (10) items. The researchers recommend the necessity of joint planning by all relevant authorities, to solve the legal, societal, technical, and administrative problems and challenges that impede the provision of transitional services for students with intellectual disabilities.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.856-859
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• 2005

This paper presents a method of constructing the highly efficiency arithmetic operation unit systems(AOUS) based on fields. The proposed AOUS is more regularity and extensibility than previous methods. Also, the proposed AOUS be able to apply basic multimedia hardware. The future research is demanded to more compact and advanced arithmetic operation algorithm.

• The KIPS Transactions:PartC
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• v.9C no.2
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• pp.163-172
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• 2002

Java Card API porvide benifit for development program based on smart card using limmited resource. This APIs does not support arithmetic operations such as modular arithmetic, greatest common divisor calculation, and generation and certification of prime number, which is necessary arithmetic in PKI algorithm implementation. In this paper, we implement class BigInteger acted in the Java Card platform because that Java Card APIs does not support class BigInteger necessary in implementation of PKI algorithm.

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.113-123
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• 2003

Many researches on the application of neural networks for making financial index prediction have proven their advantages over statistical and other methods. In this paper, a neural network model is proposed for the Buying, Holding or Selling timing prediction in stocks by the price index of stocks by inputting the closing price and volume of dealing in stocks and the technical indexes(MACD, Psychological Line). This model has an equalized multi-layer arithmetic function as well as the time series prediction function of backpropagation neural network algorithm. In the case that the numbers of learning data are unbalanced among the three categories (Buying, Holding or Selling), the neural network with conventional method has the problem that it tries to improve only the prediction accuracy of the most dominant category. Therefore, this paper, after describing the structure, working and learning algorithm of the neural network, shows the equalized multi-layer arithmetic method controlling the numbers of learning data by using information about the importance of each category for improving prediction accuracy of other category. Experimental results show that the financial index prediction using the equalized multi-layer arithmetic neural network has much higher correctness rate than the other conventional models.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1539-1547
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• 1999

캐리-세이브 가산기 (CSA)는 회로 설계 과정에서 빠른 연산 수행을 위해 가장 널리 이용되는 연산기 중의 하나이다. 그러나, 현재까지 산업체에서 CSA를 이용한 설계는 설계자의 경험에 따른 수작업에 의존하고 있고 그 결과 최적의 회로를 만들기 위해 매우 많은 시간과 노력이 소비되고 있다. 이에 따라 최근 CSA를 기초로 하는 회로 합성 자동화 기법에 대한 연구의 필요성이 대두되고 있는 상황에서, 본 논문은 연산 속도를 최적화하는 효율적인 CSA 할당 알고리즘을 제안한다. 우리는 CSA 할당 문제를 2단계로 접근한다: (1) 연산식의 멀티 비트 입력들만을 고려하여 최소 수행 속도 (optimal-delay)의 CSA 트리를 할당한다; (2) (1)에서 구한 CSA 트리의 수행 속도 증가가 최소화 (minimal increase of delay) 되는 방향으로 CSA들의 캐리 입력 포트들에 나머지 싱글 비트 입력들을 배정한다. 실제 실험에서 우리의 제안된 알고리즘을 적용하여 연산식들의 회로 속도를 회로 면적의 증가 없이 상당한 수준까지 줄일 수 있었다.Abstract Carry-save-adder (CSA) is one of the most widely used implementations for fast arithmetics in industry. However, optimizing arithmetic circuits using CSAs is mostly carried out by the designer manually based on his/her design experience, which is a very time-consuming and error-prone task. To overcome this limitation, in this paper we propose an effective synthesis algorithm for solving the problem of finding an allocation of CSAs with a minimal timing for an arithmetic expression. Specifically, we propose a two step approach: (1) allocating a delay-optimal CSA tree for the multi-bit inputs of the arithmetic expression and (2) determining the assignment of the single-bit inputs to carry inputs of the CSAs which leads to a minimal increase of delay of the CSA tree obtained in step (1). For a number of arithmetic expressions, we found that our approach is very effective, reducing the timing of the circuits significantly without increasing the circuit area.

• 한국정보교육학회:학술대회논문집
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• 2011.01a
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• pp.241-246
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• 2011

There are many discussions nowadays about utilizing smartphones to create a mobile computing educational environment. The purpose of this study is to develope an application which addresses the growing importance of mental arithmetic maps in lower elementary grades. Considering current theories on developmental characteristics for the target levels I decided that a gesture based input interface increase the users concentration and interest. Students using this application will learn and reinforce the basics of the addition, subtraction, multiplication, and division of natural numbers. By removing the limitations of time and space as afforded by the convenience of a smartphone and utilizing a gesture based input interface we can combine an application which increases users mental arithmetic speed and precision with the enjoyment of a game.

• Journal of IKEEE
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• v.17 no.3
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• pp.346-351
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• 2013

Low-cost and low-power are important requirements in mobile systems. Thus, when a floating-point arithmetic unit is needed, 24-bit floating-point format can be more useful than 32-bit floating-point format. However, a 24-bit floating-point arithmetic unit can be risky because it usually has lower accuracy than a 32-bit floating-point arithmetic unit. Consecutive floating-point operations are performed in 3D graphic processors. In this case, the verification of the floating-point operation accuracy is important. Among 3D graphic arithmetic operations, the floating-point division is one of the most difficult operations to satisfy the accuracy of $10^{-5}$ which is the required accuracy in OpenGL ES 3.0. No 24-bit floating-point divider, whose accuracy is algebraically verified, has been reported. In this paper, a 24-bit floating-point divider is analyzed and it is algebraically verified that its accuracy satisfies the OpenGL requirement.

• ETRI Journal
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• v.31 no.3
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• pp.336-338
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• 2009

This letter proposes a complexity reduction method to speed up the noiseless decoding of a bit-sliced arithmetic coding (BSAC) decoder. This scheme fully utilizes the group of consecutive arithmetic-coded symbols known as the decoding band and the significance tree structure sorted in order of significance at every decoding band. With the same audio quality, the proposed method reduces the number of calculations that are performed during the noiseless decoding in BSAC to about 22% of the amount of calculations with the conventional full-search method.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.