• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.10
• /
• pp.2059-2063
• /
• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Journal of Korean Institute of Industrial Engineers
• /
• v.24 no.3
• /
• pp.407-416
• /
• 1998

For fast Cholesky factorization, it is most important to reduce the number of nonzero elements by ordering methods. Generally, the minimum deficiency ordering produces less nonzero elements, but it is very slow. We propose an efficient implementation method. The minimum deficiency ordering requires much computations related to adjacent nodes. But, we reduce those computations by using indistinguishable nodes, the clique storage structures, and the explicit storage structures to compute deficiencies.

• Journal of the Korean Society for Industrial and Applied Mathematics
• /
• v.11 no.4
• /
• pp.47-54
• /
• 2007

In [6] some computation of spectral measures induced by normal operators $T^{*n}T^n$ was introduced. In this note we improve some computations by using spectral measures, which are related t o extremal vectors. Also, we discuss the extremal value properties and apply our spectral measure equations to moment sequences which are induced by weighted shifts.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.6
• /
• pp.974-984
• /
• 1995

This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.1
• /
• pp.101-108
• /
• 2000

The data prefetching scheme is an effective technique to reduce the main memory access latency by exploiting the overlap of processor computations with data accesses. However, if the prefetched data replicate the useful existing data in the cache memory and they are not being used in computations. performances of programs are aggravated. This phenomenon results from the lack of correct predictions for data being used in the future. When parallel programs exploit the data arrays for computations, the grain size is useful information for data prefetching scheme because it implies the range of data using in computations. Based on this information, we suggest a new data prefetching scheme exploited by the grain size of the parallel program. Simulation results show that the suggested prefetching scheme improves the performance of the simulated parallel programs due to the reduction of bus transactions as well as useful prefetching operations.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.5A
• /
• pp.503-509
• /
• 2007

Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic may VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.8
• /
• pp.1531-1536
• /
• 2016

In this paper, we propose a fast motion estimation algorithm which is important in performance of video encoding. Even though so many fast algorithms for motion estimation have been published due to its tremendous computational amount of for full search algorithm, efforts for reducing computations in motion estimation still remain. In the paper, we propose an algorithm that reduces unnecessary computations only, while keeping prediction quality the same as that of the full search. The proposed algorithm does not calculate block matching error for each candidate at once to find motion vectors but divides the calculation procedure into several steps and calculates partial sum of block errors. By doing that, we can estimate the minimum error point early and get the enhancement of calculation speed by reducing unnecessary computations. The proposed algorithm uses smaller computations than conventional fast search algorithms with the same prediction quality as full search.

• Journal of the Institute of Convergence Signal Processing
• /
• v.18 no.2
• /
• pp.62-67
• /
• 2017

In this paper, we propose a fast motion estimation algorithm which is important in performance of video encoding. Even though so many fast algorithms for motion estimation have been published due to tremendous computational amount of full search algorithm, efforts for reducing computations of motion estimation still remain. In the paper, we propose an algorithm that reduces unnecessary computations only, while keeping prediction quality the same as that of the full search. The proposed algorithm does not calculate block matching error for each candidate directly to find motion vectors but divides the calculation procedure into several steps and calculates partial sum of block errors for candidates with high priority. By doing that, we can find the minimum error point early and get the enhancement of calculation speed by reducing unnecessary computations. The proposed algorithm uses smaller computations than conventional fast search algorithms with the same prediction quality as the full search algorithm.

• Proceedings of the KSME Conference
• /
• 2001.06e
• /
• pp.299-304
• /
• 2001

The current study describes experimental and computational work on the passive control of the steady and unsteady condensation shock waves, which are generated in a transonic nozzle. The bleed slots are installed on the contoured wall of the transonic nozzle in order to control the magnitude of the condensation shock wave and its oscillations. For computations, a droplet growth equation is incorporated into the two-dimensional Navier-Stokes equation systems. Computations are carried out using a third-order MUSCL type TVD finite-difference scheme with a second-order tractional time step. Baldwin-Lomax turbulence model is employed to close the governing equations. An experiment using an indraft transonic wind tunnel is made to validate the computational results. The current computations represented well the experimental flows. From both the experimental and computational results it is found that the magnitude of the condensation shock wave in the bleed slotted nozzle is significantly reduced, compared with no passive control of solid wall. The oscillations of the condensation shock wave are successfully suppressed by a bleed slot system.

• Proceedings of the KSME Conference
• /
• 2001.06e
• /
• pp.329-334
• /
• 2001

In order to investigate the operating characteristics of a supersonic steam ejector, the axisymmetric, compressible, Reynolds-averaged, Navier-Stokes computations are performed using a finite volume method. The secondary and back pressures of the ejector system with a second throat are changed to investigate their effects on the suction mass flow. Three operation modes of the steam ejector system, the critical mode, subcritical mode and back flow mode, are discussed to predict the critical suction mass flow. The present computations are validated with some experimental results. The secondary and back pressures of the supersonic steam ejector significantly affect the critical suction mass flow. The present computations predict the experimented critical mass flow with fairly good accuracy. A good correlation is obtained for the critical suction mass flow. The present results show that provided the primary nozzle configuration and secondary pressure are known, we can predict the critical mass flow with good accuracy.