• Journal of Information Processing Systems
• /
• v.10 no.4
• /
• pp.523-542
• /
• 2014

One-dimensional arrays with subscripts formed by induction variables in real programs appear quite frequently. For most famous data dependence testing methods, checking if integer-valued solutions exist for one-dimensional arrays with references created by induction variable is very difficult. The I test, which is a refined combination of the GCD and Banerjee tests, is an efficient and precise data dependence testing technique to compute if integer-valued solutions exist for one-dimensional arrays with constant bounds and single increments. In this paper, the non-continuous I test, which is an extension of the I test, is proposed to figure out whether there are integer-valued solutions for one-dimensional arrays with constant bounds and non-sing ularincrements or not. Experiments with the benchmarks that have been cited from Livermore and Vector Loop, reveal that there are definitive results for 67 pairs of one-dimensional arrays that were tested.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.18 no.3
• /
• pp.101-108
• /
• 2023

Optimizing the performance of deep neural networks on embedded systems is a challenging task that requires efficient compilers and runtime systems. We propose a TVM-based approach that consists of three steps: quantization, auto-scheduling, and ahead-of-time compilation. Our approach reduces the computational complexity of models without significant loss of accuracy, and generates optimized code for various hardware platforms. We evaluate our approach on three representative CNNs using ImageNet Dataset on the NVIDIA Jetson AGX Xavier board and show that it outperforms baseline methods in terms of processing speed.

• Korea Information Processing Society Review
• /
• v.11 no.6
• /
• pp.8-24
• /
• 2004

OO RT programming is a technology expected to flourish in this quarter of the 21st century. Currently, its youthfulness is indicated by the insufficient availability of the support middleware and the associated API, let alone language compilers. The middleware providing fault-tolerant execution support is in its infancy. The advances in OO RT distributed programming will also enable large-scale RT simulations. The research community dealing with this technology area is expected to grow continuously for foreseeable future and consequent accelerations of the technology advances will in turn accelerate the development of many new types of sophisticated RT DC applications as well as realization of advanced types of ubiquitous computing societies.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2024.05a
• /
• pp.35-36
• /
• 2024

WebAssembly(WASM)는 웹브라우저용 바이트코드로, 다양한 언어로 작성한 코드를 손쉽게 한번에 실행할 수 있고, 기존 고수준 언어를 사용하여 웹 애플리케이션을 개발할 수 있다. WASM 은 사용자와의 실시간 소통을 필요로 하는 웹용으로 개발되었기 때문에 성능이 중요한 요소로 꼽힌다. 이 논문에서는 대표적인 WASM 컴파일러인 emscripten 과 cheerp 에 대해 각각 생성된 코드의 성능을 측정하여 최적화 정도를 비교한다. 실험 결과 emscripten 의 최적화 수준이 더욱 높았으나, 두 컴파일러의 성능 간 상충 관계가 발견되었다.

• Journal of KIISE:Software and Applications
• /
• v.32 no.12
• /
• pp.1283-1291
• /
• 2005

One of the problems in boosting Java performance using a Just-in-Time (JIT) compiler is removing redundant array bound checks. In conventional static compilers, many powerful algorithms have been developed, yet they are not directly applicable to JIT compilation where the compilation time is part of the whole running time. In the current JIT compilers, we tan use either a naive algorithm that is not powerful enough or an aggressive algorithm which requires the transformation into a static single assignment (SSA) form of programs (and back to the original form after optimization), thus causing too much overhead not appropriate for JIT compilation This paper proposes a new algorithm based on an inequality graph which can eliminate array bounds check codes aggressively without resorting to the SSA form. When we actually perform this type of optimization, there are many constraints in code motion caused by the precise exception rule in Java specification, which would cause the algorithm to miss many opportunities for eliminating away bound checks. We also propose a new method to overcome these constraints.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.48 no.12
• /
• pp.1564-1574
• /
• 1999

In order to improve the efficiency of optimizing compilers, integration of register allocation and instruction scheduling has been extensively studied. One of the promising integration techniques is register allocation based on register-reuse chains. However, the generation of register-reuse chains in the previous approach was not completely systematic and consequently it creates unnecessarily dependencies that restrict instruction scheduling. This paper proposes a new register allocation technique based on a systematic generation of register-reuse chains. The first phase of the proposed technique is to generate register-reuse chains that are optimal in the sense that no additional dependencies are created. Thus, register allocation can be done without restricting instruction scheduling. For the case when the optimal register-reuse chains require more than available registers, the second phase reduces the number of required registers by merging the register-reuse chains. Chain merging always generates additional dependencies and consequently enforces the execution order of instructions. A heuristic is developed for the second phase in order to reduce additional dependencies created by merging chains. For matrix multiplication program, the number of registers resulting from the first phase is small enough to fit into available registers for most basic blocks. In addition, it is shown that the restriction to instruction scheduling is reduced by the proposed merging heuristic of the second phase.

• The Journal of Information Technology
• /
• v.4 no.1
• /
• pp.1-7
• /
• 2001

The well-known tradeoff of Java's portability is the inefficiency of its basic execution model, which relies on the interpretation of an virtual machine. Many solutions have been proposed to overcome this problem, such as just-in-time(JIT) and offline bytecode compilers. However, JIT compiler can not avoid the overhead of runtime. since it translate bytecode into native code at runtime. And, pure offline bytecode compiler limits the ability of dynamic class loading. In this paper, we present an approach which preserves the ability to dynamically load bytecode, and is more efficient than JIT. In contrast to existing bytecode-to-C translator using the old NMI, our translator maintain complete compatibility and portability through using the Java Native Interface(JNI) standard. We have designed and implemented an translator for converting bytecode to C code with JNI.. named MyJNItool.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.5B
• /
• pp.286-294
• /
• 2007

In ASIP design, compiler is required for performance evaluation of processors being designed. The design of machine specific compiler is time consuming. This paper presents the system which generates C compiler from MDL descriptions. Compiler generation using MDL can support user retargetability and concurrency between compiler design and processor design. However, it must overcome semantics gap between compiler and machine. To handle this problem, the proposed system maps behavioral descriptions to library which contains abstract behavior for each tree pattern. Using mapped instructions and information on register file usage, the proposed system generates back-end interface function of the compiler. Generated compilers, for MIPS R3000, ARM9 cores, have been proved by application programs written in C code.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.10a
• /
• pp.487-489
• /
• 2018

This paper presents chaotic Lorenz system implementation for secure data communication applications. In this work chaotic signal is generated by a PIC18F family based microcontroller, XC8 compilers have been utilized for the compilation of C code of microcontroller program. For simulation work Matlab and Proteus platforms were utilized and finally, chaotic time waveforms, 2D and 3D chaotic attractor were obtained and secure communication waveforms were achieved successfully.

• Journal of the Korea Society of Computer and Information
• /
• v.12 no.5
• /
• pp.121-129
• /
• 2007

Scalarization is a process that a parallel construct like an array statement of Fortran 90 or FORALL of HPF is converted into sequential loops that maintain the correct semantics. Most compilers of HPF, recognized as a standard data parallel language, convert a HPF program into a Fortran 77 program inserted message passing primitives. During scalariztion, a parallel construct FORALL should be translated into Fortran 77 DO loops maintaining the semantics of FORALL. In this paper, we propose a scalarization algorithm which converts a FORALL construct into a DO loop with improved performance. For this, we define and use a relation distance vector to keep necessary dependence informations. Then we evaluate execution times of the codes generated by our method and by PARADIGM compiler method for various array sizes.