• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.291-295
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• 2008

We have developed an evaluation technique for ratio errors of current transformer (CT) comparator by using the precise standard capacitors. By applying this technique for equivalent circuit of CT comparator evaluation system, we can obtain the calculated and measured ratio errors in the CT comparator. Thus we can evaluate ratio errors of CT comparator by comparing the calculated and measured ratio errors. Because this method requires only the standard capacitors, it is simple and easy method to reliability and accuracy maintenance of CT comparator. The method was applied to CT comparator under test with the ratio error ranges of $0{\sim}{\pm}10%$. The ratio error of the CT comparator under test theoretically obtained in this method are consistent with that measured for same CT comparator under test by using wide ratio error CT within an estimated expanded uncertainty (k = 2) in the overall ratio error ranges.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.4
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• pp.412-416
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• 2008

We have developed the calibration technique of the VT comparator using nonreactive standard resistors, which evaluates both accuracy and linearity of the VT comparator by comparing experimental values with theoretical values. The correction values of VT comparator obtained by using both our method and wide ratio error VT are consistent within the expanded uncertainty. Furthermore the specification for ratio error of VT comparator have been revaluated.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.4
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• pp.437-443
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• 2008

We have developed an evaluation technique for both ratio error and phase displacement of current transformer (CT) comparator by using the precise standard capacitors and resistors. By applying this technique to equivalent circuit of CT comparator evaluation system, we can obtain the calculated and measured ratio errors (or phase displacements) in the CT comparator. Thus we can evaluate ratio errors and phase displacement of CT comparator by comparing the calculated and measured ratio errors (or phase displacements). The method was applied to CT comparator under test with the ratio errors and phase displacement ranges of $0{\sim}{\pm}10%$ and $0{\sim}{\pm}7.5$ crad, respectively. Finally we have compared the ratio error and phase displacement of the CT comparator obtained in this method with specifications of two companies.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.963-966
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• 1999

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2032-2033
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• 2008

We have developed an evaluation technique for phase displacement of current transformer (CT) comparator by using the precise standard capacitors and resistors. By applying this technique for equivalent circuit of CT comparator evaluation system, we can obtain the calculated and measured phase displacement in the CT comparator. Thus we can evaluate phase displacement of CT comparator by comparing the calculated and measured phase displacement. The method was applied to CT comparator under test with the phase displacement ranges of $0{\sim}{\pm}7.5$ crad. Finally we have compared the phase displacement of the CT comparator under test theoretically obtained in this method with the specification.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.510-510
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• 2000

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

• Proceedings of the KSR Conference
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• 1998.11a
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• pp.270-279
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• 1998

This paper presents the design of self-checking comparator using the time diversity and the application to 8 bit CPU for the implementation of fault tolerant computer system. this self-checking comparator was designed with the different time Points in which temporary faults were raised by electrical noise between duplicated functional blocks. also this self-checking comparator was simulated in the method of the fault injection using 4 bit shift register counter. we designed the duplicated Emotional block and the self-checking comparator in the single chip using the Altera EPLD and could verify the reliability and the fault detection coverage through the modeling of temporary faults ,especially intermittent faults. at the results of this research, the reliability and the fault detection coverage were implemented through the self-checking comparator using the time diversity.

• ETRI Journal
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• v.45 no.3
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• pp.534-542
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• 2023

The large amount of secondary effects in complementary metal-oxide-semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.82-88
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• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.