• Journal of Power Electronics
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• 제15권3호
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• pp.660-669
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• 2015

This paper presents a control scheme with a focus on the combination of phase disposition pulse width modulation (PDPWM) and DC capacitor voltage control for a chopper-cell based modular multilevel converter (MMC) for the purpose of eliminating the time-consuming voltage sorting algorithm and complex voltage balancing regulators. In this paper, the convergence of the DC capacitor voltages within one arm is realized by charging the minimum voltage module and discharging the maximum voltage module during each switching cycle with the assistances of MAX/MIN capacitor voltage detection and PDPWM signals exchanging. The process of voltage balancing control introduces no extra switching commutation, which is helpful in reducing power loss and improving system efficiency. Additionally, the proposed control scheme also possess the merit of a simple executing procedure in application. Simulation and experimental results indicates that the MMC circuit together with the proposed method functions very well in balancing the DC capacitor voltage and improving system efficiency even under transient states.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.256-260
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• 2001

This paper presents boost and buck and buck-boost DC-DC converter circuit topologies of high-frequency soft switching transition PWM chopper type DC-DC high power converters with a single auxiliary passive resonant snubber. In the proposed boost power converter circuits operating under a principle of ZCS turn-on and ZVS turn-off commutation schemes, the capacitor and inductor in the auxiliary passive resonant circuit works as the loss less resonant snubber. In addition to this, the switching voltage and current peak stresses as well as EMI and RFI noises can be basically reduced by this single passive resonant snubber. Moreover, it is proved that converter circuit topologies with a passive resonant snubber are capable of solving some problems of the conventional hard switching PWM processing based on high-ferquency pulse modulation operation principle. The simulation results of this converter are discussed as compared with the experimental ones. The effectiveness of this power converter with a single passive resonant snubber is verified by the 5kW experimental breadboad set up.

• Journal of Power Electronics
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• 제11권2호
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• pp.173-178
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• 2011

In order to verify the performance of brushless DC (BLDC) motors, the simulation method has been widely used. The current of a BLDC motors flows on two phase windings to obtain a constant torque. However, the freewheeling current caused by the inductance component of a BLDC motor exists at the commutation point so that the current can flow on three phase windings at the same time. Due to the changes of the excited phases, the model equations are frequently changed during BLDC motor drive operation. The model equations can be also changed by the applied switching pattern since the current path in the inverter circuit changes according to switching pattern. A BLDC motor system can utilize various switching patterns for many different purposes. However, such changes of the model equations complicate the simulation procedure. In this paper, the technique to set up model equations is proposed to ease the simulation of a BLDC motor system through an inverter circuit analysis. The proposed technique will be verified using the C language. Although this method does not provide the level of detail obtainable from commercial simulation tools like PSIM or SIMULINK, it can provide an efficient way to quickly compare various conditions.

• 전력전자학회논문지
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• 제8권4호
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• pp.336-343
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• 2003

일반적으로 브러시리스 직류 전동기의 운전을 위한 회전자의 위치정보와 여자시점 검출을 위해서는 홀센서나 엔코더와 같은 측정 장치가 요구된다. 본 논문에서는 부가적인 검출 장치를 사용하지 않고 각 상의 단자전압을 분석하여 여자 시점뿐만 아니라 회전자의 절대위치를 검출 할 수 있는 센서리스 운전 시스템을 제안한다. 더불어, 제안한 알고리즘을 10k[W]급 전동기에 적용하여 유효성과 타당성을 검증한다.

• Journal of Power Electronics
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• 제12권4호
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• pp.548-558
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• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.122-122
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• 2010

A Static Induction Thyristor (SI-Thyristor) has a great potential as power semiconductor switch for pulsed power or high voltage applications with fast turn-on switching time and high switching stress endurance (di/dt, dV/dt). However, due to direct commutation between gate driver and SI-Thyristor, it is difficult to design optimal gate driver at the aspect of impedance matching for fast gate current driving into internal SI-Thyristor. Thus, to penetrate fast positive gate current into steady off state of the SI-Thyristor, it is proposed and proceeded the internal impedance calculation of the SI-Thyristor at steady off state with the gate driver while switching conditions that are indicated applied gate voltage, $V_{GK}$ and applied high voltage across anode and cathode, $V_{AK}$.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.393-400
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• 1992

The DC(Direct-Current) servo motor has widely used for many application areas, FA(Factory Automation), OA(Office Automation) and home applications. But DC servo motor needs periodical inspection because it has brush and commutator. Recently, AC servo motor has expanded it's application areas due to for the development of the power semi-conductor and control technology. But it has large torque ripple for it's small number of commutation. And it also has cogging torque due to permanent magenet rotor. Therefore it can't run balence rotarion. Many torque ripple reduction methods are published. In this paper, phase advanced method adopted for torque ripple reduction of AC servo motor. In this research, AC servo motor torque characteristic variation surveied under the phase advance control through the computer simulation. Under the simulation, the load inertia varied from 0.0001[Kg.m$^{2}$] to 0.0314[Kg.m$^{2}$]. The result os nonlinear simulation, torque and speed ripple of AC servo motor under the phase advance control reduced approximately 50[%] and 10[%]. And maximum torque of AC servo motor under phase advance control condition increased about 5[%] as compare with fixed switching time.

• 대한전자공학회논문지
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• 제25권9호
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.295-300
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• 2001

A variety of high voltage DC power supplies employing the high frequency inverter are difficult to achieve soft switching considering a quick response and no overshoot response under the wide load variation ranges which are used in medical-use x-ray high voltage generator from 20kV to 150kV in the output voltage and from 0.5mA to 1250mA, respectively. The authors develops soft switching high voltage DC power supply designed for x-ray power generator applications, which uses series resonant inverter circuit topology with a multistage voltage multiplier instead of a conventional high voltage diode rectifier connected to the second-side of a high-voltage transformer with a large turn ratio. A constant on-time dual mode frequency control scheme operating under a principle of zero-current soft switching commutation is described. Introducing the multistage voltage multiplier, the secondary transformer turn-numbers and stray capacitance of high-voltage transformer is effective to be greatly reduced. It is proved that the proposed high-voltage converter topology with dual mode frequency modulation mode control scheme is able to be the transient response and steady-state performance in high-voltage x-ray tube load. The effectiveness of this high voltage converter is evaluated and discussed on the basis of simulation analysis and observed data in experiment.

• 제어로봇시스템학회논문지
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• 제21권10호
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• pp.910-916
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• 2015

A sensorless motor control scheme with conventional back-Electro Motive Force (EMF) sensing based on zero crossing point (ZCP) detection has been widely used in various applications. However, there are several problems with the conventional method for effectively driving sensorless brushless motors. For example, a phase mismatch of 30 degrees occurs between the ZCP and commutation time. Additionally, most of the motor speed/current controls are achieved based on a pulse width modulation (PWM) method, which generates significant noise that distracts the back-EMF sensing. Due to the PWM switching, the ZCP is not deterministic, and thus the efficiency of the motor is reduced because the phase transition points become uncertain. Moreover, the motor driving performance is degraded at a low speed range due to the effect of PWM noise. To solve these problems, an improved back-EMF detection method based on a differential line method is proposed in this paper. In addition, the proposed sensorless BLDC driver addresses the problems by using a variable voltage driver generated from a buck converter. The variable voltage driver does not generate the PWM switching noise. Consequently, the proposed sensorless motor driver improves 1) the signal-to-noise ratio of back-EMF, 2) the operation range of a BLDC motor, and 3) the torque characteristics. The proposed sensorless motor driver is verified through simulations and experiments.