• Journal of Korea Society of Industrial Information Systems
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• v.16 no.2
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• pp.85-97
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• 2011

Wireless sensor networks have emerged as one of the key enabling technologies for ubiquitous computing since wireless intelligent sensor nodes connected by short range communication media serve as a smart intermediary between physical objects and people in ubiquitous computing environment. We recognize the wireless sensor network as a massively distributed and deeply embedded system. Such systems require concurrent and asynchronous event handling as a distributed system and resource-consciousness as an embedded system. Since the operating environment and architecture of wireless sensor networks, with the seemingly conflicting requirements, poses unique design challenges and constraints to developers, we propose a very new operating system for sensor nodes based on finite state machine. In this paper, we clarify the design goals reflected from the characteristics of sensor networks, and then present the heart of the design and implementation of a compact and efficient state-driven operating system, SenOS. We describe how SenOS can operate in an extremely resource constrained sensor node while providing the required reactivity and dynamic reconfigurability with low update cost. We also compare our experimental results after executing some benchmark programs on SenOS with those on TinyOS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1027-1034
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• 2005

IEEE802.15.4a, which is started to realize the PHY layer including high precision ranging/positioning and low data rate communication functions, requires a simple and low power consumable transceiver architecture. To satisfy this requirements, the simple noncoherent on-off keying (OOK) UWB transceiver with the parallel energy window banks (PEWB) giving high precision signal processing interface is proposed. The flexibility of the proposed system in multipath fading channel environments is acquired with the pulse and bit repetition method. To analyze the bit error rate (BER) performance of this proposed system, a noise model in receiver is derived with commonly used random variable distribution, chi-square. BER of $10^{-5}$ under the line-of-sight (LOS) residential channel is achieved with the integration time of 32 ns and signal to noise ratio (SNR) of 15.3 dB. For the non-line-of-sight (NLOS) outdoor channel, the integration time of 72 ns and SNR of 16.2 dB are needed. The integrated energy to total received energy (IRR) for the best BER performance is about $86\%$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.5
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• pp.219-230
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• 2017

General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

• Korean Journal of Optics and Photonics
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• v.17 no.3
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• pp.231-239
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• 2006

In recent years, a hierarchical security architecture has been widely studied because it can efficiently protect information by allowing an authorized user access to the level of information. However, the conventional hierarchical decryption methods require several decryption keys for the high level information. In this paper, we propose a hierarchical image encryption using random phase masks and Walsh code having orthogonal characteristics. To decrypt the hierarchical level images by only one decryption key, we combine Walsh code into the hierarchical level system. For encryption process, we first perform a Fourier transform for the multiplication results of the original image and the random phase mask, and then expand the transformed pattern to be the same size and shape of Walsh code. The expanded pattern is finally encrypted by multiplying with the Walsh code image and the binary phase mask. We generate several encryption images as the same encryption process. The reconstruction image is detected on a CCD plane by a despread process and Fourier transform for the multiplication result of encryption image and hierarchical decryption keys which are generated by Walsh code and binary random phase image. Computer simulations demonstrate that the proposed technique can decrypt hierarchical information by using only one level decryption key image and it has a good robustness to the data loss such as random cropping.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.455-463
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• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.381-388
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• 2015

In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.

• Journal of Periodontal and Implant Science
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• v.32 no.1
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• pp.129-142
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• 2002

Epithelial-mesenchymal interaction plays a important role in cell growth and differentiation. This interaction is already well known to have an importance during the organ development as well as cell growth and differentiation. However, in vitro experimental model is not well developed to reproduce in vivo cellular microenvironment which provide a epithelial-mesenchymal interaction. Because conventional monolayer culture lacks epithelial-mensenchymal interaction, cultivated cells have an morphologic, biochemical, and functional characteristics differ from in vivo tissue. Moreover, it's condition is not able to induce cellular differention due to submerged culture condition. Therefore, the aims of this study were to develop and evaualte the in vitro experimental model that maintains epithelial-mesenchymal interaction by organotypic raft culture, and to characterize biologic properties of three-dimensionally reconstituted oral keratinocytes by histological and immunohistochemical analysis. The results were as follow; 1. Gingival keratinocytes reconstituted by three-dimensional organotypic culture revealed similar morphologic characteristics to biopsied patient specimen showing stratification, hyperkeratinosis, matutation of epithelial architecture. 2. Connective tissue structure was matured, and there is no difference during stratification period of epithelial 3-dimensional culture. 3. The longer of air-exposure culture on three-dimensionally reconstituted cells, the more epithelial maturation, increased epithelial thickness and surface keratinization 4. In reconstitued mucosa, the whole epidermis was positively stained by anti-involucrin antibody, and there is no difference according to air-exposured culture period. 5. The Hsp was expressed in the epithelial layer of three-dimensionally cultured cells, especially basal layer of epidermis. The change of Hsp expression was not significant by culture stratification. 6. Connexin 43, marker of cell-cell communication was revealed mild immunodeposition in reconstitued epithelium, and there is no significant expression change during stratification. These results suggest that three-dimensional oragnotypic co-culture of normal gingival keratinocytes with dermal equivalent consisting type I collagen and gingival fibroblasts results in similar morphologic and immunohistochemical characteristics to in vivo patient specimens. And this culture system seems to provide adequate micro-environment for in vitro tissue reconstitution. Therefore, further study will be focused to study of in vitro gingivitis model, development of novel perioodntal disease therapeutics and epithelial-mensenchymal interaction.