• Journal of Power Electronics
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• 제12권6호
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• 한국인터넷방송통신학회논문지
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• 제11권6호
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• pp.295-302
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• 2011

본 논문에서는 단일 주파수 망(Single Frequency Network:SFN)을 통해 ATSC(Advanced Television Systems Committee) 지상파 디지털 TV 방송을 서비스하기 위한 필요한 기술적인 사항에 대해서 고찰하고, ETRI에서 제안한 등화형 동일 채널 중계기(Equalization Digital On Channel Repeater: EDOCR)가 가지는 단점을 극복한 간섭 제거 디지털 동일 재생중계기(Interference Cancellation Digital On Channel Regenerative Repeater: IC-DOCR)을 제안한다. 제안한 IC-DOCR은 EDOCR의 장점인 전송로에 의해 야기된 잡음 및 다중경로 신호를 제거하므로 우수한 송신품질을 유지한다. 또한, EDOCR 단점인 낮은 송수신 안테나의 격리도(isolation)를 확보하기 위해서 수신 신호의 8-VSB 복조를 이용한 간섭제거 알고리즘을 사용하여 송신 출력의 제한을 극복할 수 있다. 전산 실험을 통해서 제안된 시스템의 성능을 분석하고 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.293-296
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• 2002

This paper proposes new driving methods for designing a driver independent of the current property of organic light emitting diodes (OLED) displays. The proposed methods are the Look-Up Table (LUT) and the Pulse Width Modulation (PWM). The LUT is used to handle the amount of the current for driving the OLED display panel and the PWM is applied to represent the gray scale on the OLED display panel. Segment and common drivers were implemented using delay circuits to prevent short-circuit current and a DC-DC converter was designed to supply the drivers with a power source. In particular, tile proposed methods are used for the manufacturing of 1.8" 128$\times$128 dot passive matrix OLED display panel. The designed circuit was fabricated using 0.6w, 2-poly, 3-metal, CMOS process and applied to the Personal Communication System (PCS) phone successfully.ully.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.410-413
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• 2000

This paper suggests a methodology in which control signals for high-level synthesis are generated from SDL specification. SDL is based on EFSM(Extended Finite State Machine) model. Data path and control part are partitioned into representing data operations in the from of scheduled data flow graph and process behavior of an SDL code in forms of an abstract FSM. Resource allocation is performed based on the suggested architecture model and local control signals to drive allocated functional blocks are incorporated into an abstract FSM extracted from an SDL process specification. Data path and global controller acquired through suggested methodology are combined into structural VHDL representation and correctness of behavior for final circuit is verified through waveform simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.481-487
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• 2016

A new two-line based inversion driving method is introduced for low power display-driver ICs. By inserting a timing offset between the chopper stabilization and the alternation of LCD polarity, we can reduce power consumption without noticeable degradation in the display quality. By applying the proposed scheme to 12" LCD applications, we achieved 7.5% and 27% power saving in the display-driver IC with white and black patterns, respectively.

• Journal of information and communication convergence engineering
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• 제9권1호
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• pp.74-77
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• 2011

PSPICE modeling of a commercial LED driver IC (TOP245P) and PC817A optocoupler is proposed for the switch-mode power supply (SMPS) (applicable to LED driver) design and simulation. An analog behavioral model of the TOP245P IC including the shunt regulator, under-voltage(UV) detection, over-voltage(OV) shut-down and SR flip-flop is developed by using PSPICE. The empirical equation of PC817A current transfer ratio (CTR) is fitted from the datasheet of PC817A. Two types of SMPSs are simulated with the averaged-model and switching-model. The simulation results by the proposed PSPICE models are in good agreement with those in the data sheet and an experimental data.

• 전자공학회논문지
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• 제53권7호
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• pp.131-137
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• 2016

본 논문에서는 기존의 2D IC의 성능을 개선하고 3D IC의 집적도와 전기적인 특성을 개선하기 위한 목적으로 연구되고 있는 TSV (Through Silicon Via)의 임피던스를 해석하였다. 향후 Full-chip 3D IC 시스템 설계에서 TSV는 매우 중요한 기술이며, 높은 집적도와 광대역폭 시스템 설계를 위해서 TSV에 대한 전기적인 특성에 관한 연구가 매우 중요하다. 따라서 본 연구에서는 Full-chip 3D IC를 설계하기 위한 목적으로 다중 TSV-to-TSV에서 거리와 주파수에 따른 TSV의 임피던스 영향을 해석하였다. 또한 이 연구 결과는 Full-chip 3D IC를 제조하기 위한 반도체 공정과 설계 툴에 적용할 수 있다.

• Journal of information and communication convergence engineering
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• 제12권1호
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• 전자공학회논문지A
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• 제30A권1호
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• pp.73-85
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• 1993

This paper presents a design and implementation of CAD(Computer-Aided Design) system with tools and design environments for IC(Intergrated Circuits)design. The CAD system can be easily installed in various sites with limited resources, since most CAD tools and design environments are available in the public-domain and Unix & X Window-based PC-386 and Workstation is used for the hardware platform. In order to improve the flexibility of the CAD system, objects are defined in the context of tools and environments` and object tables are programmed to describe the integration of CAD tools and design environments. During the execution, tool-objects deal with intertool communication and round-robin mechanism to incrementally control the execution of CAD tools. The IC design of LPC(Linear Predictive Coding) Speech Synthesizer is carried out to find out improvements and bugs of the CAD system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2039-2041
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• 2001

According to the deregulation of governments in the world, the power industries of United State and European nations are proceeding remote meter reading and remote load control. But the core technology of multifunctional electronic meter implemented by programmable one-chip IC, which can be the right answer of ail the power industy's efforts is now still under development in the advanced countries. Implementation of smallest size, lowest price three-phase meter with features which enable distribution automation such as bidirectional communication. The three phase metering IC and meter can be used as metering, automatic meter reading and transformer monitoring. Prepayment billing system.