• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.754-766
• /
• 2010

In the wireless communication protocols, a network device is responsible for the operation of lower-layers. The network device consists of hardware and software modules, so it can be designed using system-on-chip simulator. The simulator design needs the support of a network simulator as well as system-on-chip simulator, because the network device interact with various higher layer communication protocols. Therefore the co-simulator can become a development environment of the network device through the combining of them. In this paper we propose a co-simulator combining these two simulators. The proposed co-simulator does not degrade performance due to integrations. Also, it is easy to integrate them because the implementation of the kernel is independent.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.1
• /
• pp.57-64
• /
• 2006

Multiprocessor system on chip (MPSoC) platforms has set a new innovative trend for the SoC design. Quality of service parameters and performance matrix are leading to the adoption of new design methodology for SoC, which will incorporate highly scalable, reusable, predictable, cost and energy efficient platform not only for underlying communication backbone but also for the entire system architecture of NOC. Like the layered architecture for the communication backbone of NOC, we have proposed the entire system architecture for NOC to be a seven layered architecture in itself. Such a platform can separate the domain specific issues which will model concurrency along with the synchronization issues more effectively. For such a layered architecture, model of computation will provide a framework to that can model concurrency and synchronization issues which are natural for any application. Therefore it becomes extremely important to use a right computation model in a specific NOC region.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.25-32
• /
• 2009

Recently, research for Network-on-chip(NoC) is progressing. However, due to the increase of system complexity and demand on high performance, conventional copper-based electrical interconnect would be faced with the design limitation of performance, power, and bandwidth. As an alternative to these problems, combined use of Electrical Interconnects(EIs) and Optical Interconnects(OIs) has been introduced. In this paper we propose efficient routing optimization strategy and hybrid switch architecture, which use OIs for critical path and EIs for non-critical path. The proposed method shows up to 25% performance improvement and 38% power reduction.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.2
• /
• pp.55-67
• /
• 2005

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate Performance estimation. Since local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology arc validated by two real -life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

• Journal of Korea Multimedia Society
• /
• v.10 no.1
• /
• pp.49-57
• /
• 2007

Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.131-139
• /
• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of IKEEE
• /
• v.8 no.1 s.14
• /
• pp.145-151
• /
• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.4A
• /
• pp.415-422
• /
• 2004

DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz down-conversion mixer for DSRC communication system was designed and fabricated using 0.8 ${\mu}{\textrm}{m}$ SiGe HBT process technology and RF/LO matching circuits, RF/LO input balun circuits, and If output balun circuit were all integrated on chip. The chip size of fabricated mixer was 1.9 mm${\times}$1.3 mm and the measured performance was 7.5 ㏈ conversion gain, －2.5 ㏈m input IP3, 46 ㏈ LO to RF isolation, 56 ㏈ LO to IF isolation, current consumption of 21 mA for 3.0 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.4A
• /
• pp.350-357
• /
• 2005

DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz up-conversion mixer for DSRC communication system was designed and fabricated using 0.8 m SiGe HBT process technology and IF/LO/RF matching circuits, IF/LO input balun circuits, and RP output balun circuit were all integrated on chip. The chip size of fabricated mixer was $2.7mm\times1.6mm$ and the measured performance was 3.5 dB conversion gain, -12.5 dBm output IP3, 42 dB LO to If isolation, 38 dB LO to RF isolation, current consumption of 29 mA for 3.0 V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.4
• /
• pp.508-514
• /
• 2020

To implement the continuously evolving mobile communication standards such as Long Term Evolution (LTE) and 5G, the Software Defined Radio (SDR) concept provides great flexibility and efficiency. For many years, a high-end Digital Signal Processor (DSP) System on Chip (SoC) has been developed to support multicore and various hardware coprocessors. This paper introduces the implementation of the SDR platform hardware using TI's TCI663x chip. Using the platform, LTE transport channel is implemented by interworking multicore DSP with Bit rate Coprocessor (BCP) and Turbo Decoder Coprocessor (TCP) and the performance is evaluated according to various implementation options. In order to evaluate the performance of the implemented LTE transport channel, LTE base station system was constructed by combining FPGA main board for physical channels, SDR platform board, and RF & Antenna board.