• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.838-840
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• 1998

$BiNbO_4$ ceramics with 0.06wt% CuO, 0.1wt% $V_{2}O_{5}$ sintered at $900^{\circ}C$. The strip line chip filter has been design and fabricated by screen printing with silver electrode after tape casting. The characteristics of the fabricated filters were compared with the simulated results. In the strip line chip filter, insertion loss value of band pass width was 3.65[dB] and return loss was 8.9[dB] and center frequency was similar that simulation results.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.292-298
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• 1991

A new 6-axis robot controller with a high-speed 32-bit floating-point DSP TMS32OC30 has been developed in Samsung Electronics. The controller composed of Intel 80386 microprocessor for the main controller, and TKS32OC30 DSP chip for joint position controller. The characteristics of the controller are high sampling rate of 200us and fast reponsibility. The main controller supports MS-DOS, kinematics, trajectory planning, and sensor fusion functions which are vision, PLC, and MAP. The one high speed DSP chip is used for controlling 6 axes of a robot in 200us simultaneously. The control law applied is PID controller including a velocity feedforvard in joint position controller. The performance tests, such as command following, CP, were conducted for the controller integrated with a 6 axes robot developed in Samsung Electronics. The results showed a good performance. This controller can also perform the system control with other controllers, the communication with high priority controllers, and visual information processing.

• Journal of Advanced Marine Engineering and Technology
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• v.31 no.6
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• pp.777-783
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• 2007

In this work, a highly integrated downconverter MMIC employing HBT(heterojunction bipolar transistor) was developed for application to one chip tranceiver solution of Ku-band commercial wireless communication system. The downconverter MMIC (monolithic microwave integrated circuit) includes mixer filter. amplifier and input/output matching circuit. Especially, spiral inductor structures employing SiN film were used for a suppression of LO and its second harmonic leakage signals. Concretely, they were properly designed so that the self-resonance frequency was accurately tuned to LO and its second harmonic frequency, and they were integrated on the downconverter MMIC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1089-1095
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• 2005

This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.687-694
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• 1999

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1776-1778
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• 2000

The demands placed on portable wireless communication equipment include low cost, low supply voltage, low power, dissipation, low noise, high frequency of operation, and low distortion. These design requirements cannot be met satisfactorily in many cases without the use of RF inductors. However, implementing the inductor on-chip has been regarded as an impractical task because of excessive substrate capacitance and substantial resistive losses due to metallization and the conductive silicon substrate. Hence, there is a great incentive to design, optimize, and model spiral inductors on Si substrate. So, we analyzed a chip inductors using electromagnetic analysis and established a set of design rules for rectangular spiral inductors.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.9
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• pp.712-718
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• 1991

In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.

• Journal of information and communication convergence engineering
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• v.2 no.1
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• pp.5-8
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• 2004

DS-COMA is now a matured multiple access technology that utilizes spreading codes for user separation. In this paper, we attempt to improve the performance of a multiuser DS-COMA system with a unique chip shaping code called Carrier Interferometry (CI) code. The CI codes exhibit an excellent correlation property that can be used in many applications. In DS-COMA with CI codes (CI/DS-COMA), the symbols are spread by a spreading code and then the chip signals are shaped using a CI code. Due to the correlation property of the CI code, a diversity gain from the shaped chip signals is achieved and the performance of DS-COMA is significantly improved. Comparison study demonstrates that the DS-COMA with CI outperforms the conventional DS-COMA system in multiuser environments.

• Journal of information and communication convergence engineering
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• v.19 no.3
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• pp.175-179
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• 2021

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

• International journal of advanced smart convergence
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• v.11 no.2
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.