• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.287-288
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• 2014

본 논문에서는 3레벨 4레그 컨버터에서 커먼 모드 전압(Common-mode Voltage, CMV)을 저감하기 위한 삼각파 비교 전압 변조 기법을 제안하였다. 제안한 PWM 방법은 매우 직관적이고, DSP 제어 시스템에서 쉽게 구현할 수 있다. SVPWM, SPWM의 스위칭 패턴 분석을 통하여 CMV 저감을 위한 4번째 레그(f상)의 극 전압 패턴을 제안하였고, 해당하는 f상 극 전압의 합성을 위하여, f상 양/음의 극 전압 지령 값을 계산하였다. 또한 a, b, c상 전압 왜곡을 막기 위한 옵셋 전압을 유도하였다. 제안한 PWM 방법의 유효성은 모의실험과 실험 결과를 통하여 검증되었다. 제안된 방법에서 CMV의 첨두치 및 스위칭 수는 SVPWM 방법에 비하여 각각 33%, 25%로 대폭 감소하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.4
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• pp.587-593
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• 2021

Since 2017, a total of 29 fire accidents have occurred in energy storage systems (ESSs) as of June 2020. The common mode voltage (CMV) is one of the electrical hazards that is assumed to be a cause of those fire accidents. Several cases of CMV that violate the allowable insulation level of a battery section are being reported in actual ESS operation sites with △-Y winding connections. Thus, this paper evaluates the characteristics of CMV. An ESS site was modeled with an AC grid, PCS, and battery sections using PSCAD/EMTDC software. As a result of a simulation based on the proposed model, it was confirmed that characteristics of CMV vary significantly and are similar to actual measurements, depending on the grounding method of the internal transformer for PCS. The insulation level of the battery section may be severely degraded as the value of CMV exceeds the rated voltage in case of a grounding connection. It was found that the value of CMV dramatically declines when the internal transformer for PCS is operated as non-grounding connection, so it meets the standard insulation level.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.9-10
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• 2017

본 논문은 MMC 토플로지에서 EMI 노이즈와 누설 전류를 발생시키는 커먼모드 전압(Commom Mode Voltage, CMV)을 스위칭 스테이트 해석을 통해 일반화 하고 이를 저감할 수 있는 기법을 제안한다. 이러한 CMV에 관한 해석과 저감 기법은 시뮬레이션으로 타당성을 검증하였다.

• Journal of Power Electronics
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• v.19 no.4
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• pp.907-921
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• 2019

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2258-2271
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• 2016

In this paper, some crucial performance characteristics related to the operational reliability of the post-fault Pulse Width Modulated (PWM) rectifiers, such as line current harmonic distortion, Common Mode Voltage (CMV), and current stress on the capacitors, are fully investigated. The aforementioned performance characteristics of post-fault rectifiers are highly dependent on the utilized space vector modulation (SVM) schemes, which are also examined. Detailed analyses of the three most commonly used SVM schemes for post-fault PWM rectifiers are provided, revealing the major differences in terms of the zero vector synthesis approaches. To compare the performances of the three SVM schemes, the operating principles of a post-fault rectifier are presented with various SVM schemes. Using analytical and numerical methods in the time domain, the performances of the line current distortion, common mode voltage and capacitor current are evaluated and compared for each SVM scheme. The proposed analysis demonstrates that the zero vector synthesis approaches of the considered methods have significant impacts on the performance characteristics of rectifiers. In addition, the advantages and disadvantages of the proposed SVM schemes are discussed. The experimental results verify the effectiveness and validity of the proposed analysis.

• Journal of Power Electronics
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• v.18 no.1
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• pp.81-91
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• 2018

This paper proposes a double line voltage synthesis (DLVS) strategy for three-to-five phase direct matrix converters. In the proposed strategy, the input and expected output voltages are divided into 6 segments and 10 segments, respectively. In addition, in order to obtain the maximum voltage transfer ratio (VTR), the input line voltages and "source key" should be selected reasonably according to different combinations of input and output segments. Then, the corresponding duty ratios are calculated to determine the switch sequences in different segment combinations. The output voltages and currents are still sinusoidal and symmetrical with little lower order harmonics under unbalanced or distorted input voltages by using this strategy. In addition, the common mode voltage (CMV) can be suppressed by rearranging some of the switching states. This strategy is analyzed and studied by a simulation model established in MATLAB/Simulink and an experimental platform, which is controlled by a DSP and FPGA. Simulation and experimental results verify the feasibility and validity of the proposed DLVS strategy.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.568-574
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• 2020

Recently, the installation of energy storage systems (ESSs) that have a range of functions, such as power stabilization of renewable energy sources, demand control, and frequency regulation, has been increasing annually. On the other hand, since the fire accident of ESS occurred at Gochang Power Test Center in August 2017, 29 fire accidents with significant property losses have occurred, including the Gyeongsan substation and Kunsan PV power plant. Because these fire accidents of ESS are arisen regardless of the season and capacity of ESS, an analysis of the fault characteristics in ESS is required to confirm the causes of the fire accidents accurately and ensure the safety of the ESS. This paper proposes the modeling of ESS using PSCAD/EMTDC S/W to identify the fault characteristics and ensure the safety of the ESS. From the simulation results of fault characteristics based on various scenarios, it is clear that the insulation of ESS may be breakdown due to the largely occurring CMV (common mode voltage). Furthermore, the CMV between the PCS and battery can be reduced, and the insulation breakdown of ESS can be prevented if an SPD (surge protect device) is installed in the battery and PCS sides, respectively.

• Journal of Power Electronics
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• v.19 no.4
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• pp.968-979
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• 2019

Recently, there has been increased interest in the study of multiphase machines due to their higher fault-tolerant capability when compared to their conventional three-phase counterparts. For six-phase machines, stator windings configured with a single isolated neutral (1N) provide significantly more post-fault torque/power than two isolated neutrals (2N). Hence, this configuration is preferred in applications where post-fault performance is critical. It is well known that min-max injection has been commonly used for three-phase and multiphase machines in healthy condition to maximize the modulation limit. However, there is a lack of discussion on min-max injection for post-fault condition. Furthermore, the effects in terms of the common-mode voltage (CMV) in modulating signals has not been discussed. This paper investigates the effect of min-max injection in post fault-tolerant control on the voltage and speed limit of a symmetrical six-phase induction machine with single isolated neutral. It is shown that the min-max injection can minimize the amplitude of reference voltage, which maximizes the modulation index and post-fault speed of the machine. This in turn results in a higher post-fault power.