• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.9 s.100
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• pp.957-963
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• 2005

This paper presents technique of wideband TIA for optical communication systems using TSMC 0.25 ${\mu}m$ CMOS RF-Mixed mode. In order to improve bandwidth characteristics of an TIA, we use active inductor shunt peaking to cascode and common-source configuration. The result shows the 37 mW and 45 mW power dissipation with 2.5 V bias and 61 dB$\Omega$ and 61.4 dB$\Omega$ transimpedance gain. And the -3 dB bandwidth of the TIA is enhanced from 0.8 GHz to 1.45 GHz in cascode and 0.61 GHz to 0.9 GHz in common-source. And the input noise current density is $5 pA/\sqrt{Hz}$ and $4.5 pA/\sqrt{Hz}$, and -10 dB out put return loss is obtained in 1.45 GHz. The total size of the chip is $1150{\times}940{\mu}m^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Journal of Power Electronics
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• v.16 no.2
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• pp.654-665
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• 2016

The pumping of electric power from photovoltaic (PV) farms is normally carried out using transformers, which require heavy mounting structures and are thus costly, less efficient, and bulky. Therefore, transformerless schemes are developed for the injection of power into the grid. Compared with the H4 inverter topology, the H6 topology is a better choice for pumping PV power into the grid because of the reduced common mode current. This paper presents how the perturb and observe (P&O) algorithm for maximum power point tracking (MPPT) can be implemented in the H6 inverter topology along with the improved sinusoidal current injected to the grid at unity power factor with the average current mode control technique. On the basis of the P&O MPPT algorithm, a power reference for the present insolation level is first calculated. Maintaining this power reference and referring to the AC sine wave of bus bars, a sinusoidal current at unity power factor is injected to the grid. The proportional integral (PI) controller and fuzzy logic controller (FLC) are designed and implemented. The FLC outperforms the PI controller in terms of conversion efficiency and injected power quality. A simulation in the MATLAB/SIMULINK environment is carried out. An experimental prototype is built to validate the proposed idea. The dynamic and steady-state performances of the FLC controller are found to be better than those of the PI controller. The results are presented in this paper.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.333-336
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• 2002

An alternative CMOS implementation of a multi-output four-terminal floating nullor (FTFN) with constant-g$_{m}$ rall-to-rail input stage is proposed. This presented circuit is based on the advantages of a complementary transconductance amplifier and class AB dual translinear cell circuit that comes up with wide bandwidth. The constant-g$_{m}$ characteristic is controlled by the maximum-current selection circuits, maintaining the smooth response over the change of input common mode voltage. The circuit performances are confirmed through HSPICE simulations. A current-mode multifunction filter is used to exhibit the potentiality of this proposed scheme.eme.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.

• Journal of Power System Engineering
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• v.11 no.4
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• pp.12-17
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• 2007

Recently, many small and medium size diesel vehicles have been equipped with turbocharger and EGR system to get high performance and reduce $NO_x$ emissions but its application to heavy-duty diesel engine is not common yet. In this work, the simulation model for EURO-3 engine was developed using WAVE and then its performance and emission level were verified by comparing with experimental results. The possibility of current EURO-3 engine equipped with LPL EGR system which would be satisfied the EURO-5 regulation are examined. ESC 13 mode was chosen as the primary engine test mode, and the injection timing and fuel quantity were changed to compensate the lost engine performance caused by EGR. The system developed in this study shows that the current EURO-3 engine could satisfy EURO-5 $NO_x$ regulation by applying LPL EGR.

• Journal of Power Electronics
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• v.4 no.4
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• pp.197-204
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• 2004

Two-stage Power-Factor-Correction (PFC) converters are the most common circuits for drawing sinusoidal and in phase current waveforms from an ac source with a good regulated output voltage. The first stage is a boost PFC converter with average-current-mode control for achieving the near-unity power factor and the second stage is a forward converter with voltage-mode control to regulate the output voltage. Stability analysis and design methods of two-stage PFC converters have previously been discussed using linear models. Recently, new nonlinear phenomena have been detected in pre-regulator boost PFC circuits and a new nonlinear model has been proposed for pre-regulated PFC converters. Therefore, investigation of two-stage PFC converters from the nonlinear viewpoint becomes important because the second stage DC/DC converter adds more complexity to the circuit. So, this paper introduces a study of the stability of two-stage PFC converters. A novel nonlinear model of two-stage PFC converters is proposed. Then, a stability analysis is made based upon this nonlinear model. The high correspondence between the simulated and experimental results confirms our analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.4
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• pp.275-282
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• 2022

In this study, an inverter system connected to a grid through a paralleled LCL filter is proposed. The system consists of two inverters paralleled and operated with interleaved PWM for powering up and performance improvement. Two LCL filters have two separate filter inductors and one set of filter capacitor and grid inductor in common. The differential mode current circulates through two inverters and two filter inductors. The differential mode current is removed from the filter capacitor and the power grid. Accordingly, performance improvement can be achieved due to the reduced currents in the filter capacitor and the reduced harmonics into a grid. A single-phase prototype has been made and tested, and the proposal has been verified.

• Journal of Power Electronics
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• v.15 no.4
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• pp.920-928
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• 2015

Transformerless solar inverters have a higher efficiency than those with an isolation link. However, they suffer from a leakage current issue. This paper proposes a family of single phase six-switch transformerless inverter topologies with an ac bypass circuit to solve the leakage current problem. These circuits embed two unidirectional freewheeling current units into the midpoint of a full bridge inverter, to obtain a freewheeling current path, which separates the solar panel from the grid in the freewheeling state. The freewheeling current path contains significantly fewer devices and poor performance body diodes are not involved, leading to a higher efficiency. Meanwhile, it is not necessary to add a voltage balancing control method when compared with the half bridge inverter. Simulation and experiments are provided to validate the proposed topologies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.82-90
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• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.