• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.3
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• pp.452-456
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• 2016

In this paper, a dual-channel readout amplifier array is realized in a standard $0.18{\mu}m$ CMOS technology for the applications of panoramic scan LADAR systems. Each channel consists of a PIN photodiode with 0.9 A/W responsivity and a 1.0 Gb/s readout amplifier(ROA). The proposed ROA shares the basic configuration of the previously reported feedforward TIA, except that it exploits a replica input to exclude a low pass filter(LPF), thus reducing chip area and improving integration level, and to efficiently reject common-mode noises. Measured results demonstrate that each channel achieves $70dB{\Omega}$ transimpedance gain, 829 MHz bandwidth, -22 dBm sensitivity for $10^{-9}BER$, -34 dB crosstalk between adjacent channels, and 45 mW power dissipation from a single 1.8 V supply.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.245-246
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• 2015

본 논문에서는 삼중 델타 전원과 새로운 커먼-모드 필터 결선을 통해 스위칭에 의한 고조파를 저감하는 방법을 제안한다. PWM에 의해 생성되는 측대파 고조파(Sideband harmonics) 위상을 분석함으로써, 인터리빙 운전 시 삼중 델타 전원 연결과 제안된 커먼모드 필터가 측대파 고조파 전류를 크게 저감할 수 있음을 보인다. 3개의 고정자 권선을 가지는 영구자석 전동기를 이용하여 제안된 필터의 유효성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.346-347
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• 2020

This paper presents the two combination methods for leakage current reduction in photovoltaic system PCS. The leakage current in the photovoltaic system generated from the parasitic capacitance existing between the photovoltaic system and ground relevance to common mode voltage caused by PWM switching. Firstly, Leakage current reduced by a PWM method using two carriers with 180-degree phase different. Secondly, the leakage current is more reduced by connecting LCL filter to the mid-point of DC link. This combining method is revealed in PSIM simulation with 1 uF parasitic capacitance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.3
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• pp.32-43
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• 2014

This paper presents the intra capacitance modeling according to the winding method, section bobbin and coil structure for hybrid choke coil capable of the EMI attenuation of broad bands from lower frequency bands to higher frequency bands and high frequency type common-mode choke coil capable of the EMI attenuation of high frequency band used in the EMI Block of LED-TV SMPS. In case of high frequency type CM choke coil, it can be explained the parasitic capacitance of A type and section bobbin type winding methods among them is much smaller than the other. The first resonant frequency of the proposed CM choke coil tends to increase as the parasitic capacitance becomes small and its impedance characteristics also show improved performance as the first resonant frequency increases. In case of hybrid choke coil using rectangular copper wire, it has investigated its parasitic capacitance compared to CM choke coil of conventional toroidal type becomes small. Also it has confirmed through the experiment results that CE margin and RE margin in frequency bands 0.5MHz to 5MHz and 30MHz to 200MHz are respectively 10dB and 15dB greater than that of conventional type in case of one stage EMI filter structure adopting hybrid choke coil compared to two stage EMI Filter structure using two of each CM choke coil used in the lower and higher frequency bands or two of CM choke coil used in only the lower frequency bands. In the future, the hybrid choke coil and CM choke coil of high frequency type show it can be practically used in not only LED/LCD-TV SMPS but also several applications such as LED Lighting, Laptop Adapter, Server Power Supply and so on.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.2 s.257
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• pp.188-194
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• 2007

New diesel engines equipped with common-rail injection systems and advanced engine management control allow drastic decreases in the production of particulate matters and nitrogen oxides with a significant advantage in terms of the fuel consumption and $CO_2$ emissions. Nevertheless, the contribution of exhaust gas after treatment in the ultra low emission vehicles conception has become unavoidable today. Recently the passive type DPF(Diesel Particulate Filter Trap) system for diesel passenger vehicle has been manufactured into mass production from a French automotive maker since the year of 2000. This passive DPF system fully relies on the catalytic effects from additives blended into the diesel fuel and additives injected into the DPF system. In this study, the effects of PM regeneration in the commercial diesel passenger vehicle with the passive type DPF system were investigated in chassis dynamometer CVS(constant volume sampler)-75 mode. As shown in this experimental results, the DPF regeneration was observed at temperature as low as $350^{\circ}C$. And the engine-controlled the DPF regeneration founded to be one of the most promising regeneration technologies. Moreover, the durability of this DPF system was evaluated with a season weather in terms of the differential pressure and exhaust gas temperature traces from a road test during the total mileage of 80,000km.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.15-18
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• 2013

This paper presents an analog front-end for electroencephalogram(EEG) signal processing. Since EEG signals are typically weak and located at very low frequencies, it is imperative to implement an amplifier with high gain, high common-mode rejection ratio(CMRR) and good noise immunity at very low frequencies. The analog front-end of this paper consists of a programmable-gain instrumentation amplifier and a band-pass filter. A frequency chopping technique is employed to remove the low-frequency noise. The circuits were fabricated in 0.18um CMOS technology and measurements showed that the analog front-end has the maximum gain of 60dB and >100dB CMRR over the programmable gain range.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.342-347
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• 2017

We present a precision instrument amplifier (IA) designed for bio-potential acquisition. The proposed IA employs a capacitively coupled instrument amplifier (CCIA) structure to achieve a rail-to-rail input common-mode range and low gain error. A positive feedback loop is applied to boost the input impedance. Also, DC servo loop (DSL) with pseudo resistors is adopted to suppress electrode offset for bio-potential sensing. The proposed amplifier was designed in a $0.18{\mu}m$ CMOS technology with 1.8V supply voltage. Simulation results show the integrated noise of $1.276{\mu}Vrms$ in a frequency range from 0.01 Hz to 1 KHz, 65dB SNR, 118dB CMRR, and $58M{\Omega}$ input impedance respectively. The total current of IA is $38{\mu}A$. It occupies $740{\mu}m$ by $1300{\mu}m$ including the passive on-chip low pass filter.