• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of Power Electronics
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• v.17 no.3
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• pp.621-631
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• 2017

A KY converter integrated with a conventional synchronously rectified (SR) boost converter and a coupled inductor is presented in this paper. This improved KY converter has the following advantages: 1) the two converters use common switches; 2) the voltage gain of the KY converter can be improved due to the integration of a boost converter and a coupled inductor; 3) the leakage inductance of the coupled inductor is utilized to achieve zero voltage switching (ZVS); 4) the current stress on the charge pump capacitors and the decreasing rate of the diode current can be limited due to the use of the coupled inductor; and 5) the output current is non-pulsating. Moreover, the active switches are driven by using one half-bridge gate driver. Thus, no isolated driver is needed. Finally, the operating principle and analysis of the proposed converter are given to verify the effectiveness of the proposed converter.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.653-656
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• 2003

We have designed embedded web sewer system and ported Linux operating system version 2.4.5 at our system. And then We implemented to control and monitor widely separated hardware and implemented to monitor widely separated image using CMOS image sensor HV7131B. Web server is the Boa web server with General Public License. We designed for this system using of Intel's SA1110 ARM core base processor and connecting input and output device at GPIO port of SA1110. Device driver of General purpose I/O for Embedded Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• Nuclear Engineering and Technology
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• v.48 no.2
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• pp.470-481
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• 2016

Field-programmable gate arrays (FPGAs) have received much attention from the nuclear industry as an alternative platform to programmable logic controllers for digital instrumentation and control. The software aspect of FPGA development consists of several steps of synthesis and refinement, and also requires verification activities, such as simulations that are performed individually at each step. This study proposed an integrated software-testing framework for simulating all artifacts of the FPGA software development simultaneously and evaluating whether all artifacts work correctly using common oracle programs. This method also generates a massive number of meaningful simulation scenarios that reflect reactor shutdown logics. The experiment, which was performed on two FPGA software implementations, showed that it can dramatically save both time and costs.

• Journal of Korean Medical classics
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• v.20 no.1
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• pp.85-102
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• 2007

Zhang thinks human life consists of body(形) and Shen(神 spirit). Body comes from Jing(精), Shen comes from Qi(氣). The common basic of body and Shen is Qi. Thus the elements of human life are Jing, Qi and Shen. Among the three life elements, Jing is the lowest level. To preserve Jing is the key to Life Care. To preserve Jing, we should rest body and Shen, and Shen rules body, so to rest Shen is necessary to preserve Jing. When Jing is full, it converts to Qi, and Qi converts to Shen. Shen is ruled by mind(心), so mind sould be quiet. There is a gate through which Jing and Qi pass. It is called Mingmen(命門), and it sould be closed tight to preserve Jing.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.595-598
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• 2014

원전 디지털 계측제어시스템에서 공통원인고장(Common cause failure)의 발생 가능성이 증가함에 따라 이를 방지하기 위해 프로그래머블 논리소자(Field Programmable Gate Array)를 이용한 제어기가 개발되어 활용되고 있다. 그러나, FPGA-기반의 제어기를 구현하는데 사용되는 하드웨어 기술 언어는 그래픽 언어를 이용한 PLC 기반의 개발을 하던 대부분의 원전 계측제어 엔지니어에게 친숙하지 않아 제어기의 구현에 어려움이 있다. 따라서 엔지니어에게 친숙한 그래픽 언어를 이용하여 FPGA 용 제어 프로그램을 작성할 수 있는 통합개발환경이 필요하다. 본 논문에서 구현한 VerilogLinker 는 제어프로그램의 개발을 위한 통합개발환경의 일부로 통합개발환경을 이용한 제어 프로그램의 개발과정 중에서 생성된 Verilog 파일을 FPGA 공급자가 제공하는 상용 소프트웨어인 Libero SoC 와 연결하는 기능을 제공한다.

• The Journal of Korea Robotics Society
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• v.16 no.3
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• pp.245-249
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• 2021

In this paper, we present novel simulation contents for drone racing and autonomous flight of drone. With Depth camera and SLAM, we conducted mapping 3 dimensional environment through RTAB-map. The 3 dimensional map is represented by point cloud data. After that we recovered this data in Unreal Engine. This recovered raw data reflects real data that includes noise and outlier. Also we built drone racing contents like gate and obstacles for evaluating drone flight in Unreal Engine. Then we implemented both HITL and SITL by using AirSim which offers flight controller and ROS api. Finally we show autonomous flight of drone with ROS and AirSim. Drone can fly in real place and sensor property so drone experiences real flight even in the simulation world. Our simulation framework increases practicality than other common simulation that ignore real environment and sensor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.5
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.16-23
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• 2022

Cardiac disease is the most common cause of death worldwide. Therefore, detection and classification of electrocardiogram (ECG) signals are crucial to extend life expectancy. In this study, we aimed to implement an artificial intelligence signal recognition system in field programmable gate array (FPGA), which can recognize patterns of bio-signals such as ECG in edge devices that require batteries. Despite the increment in classification accuracy, deep learning models require exorbitant computational resources and power, which makes the mapping of deep neural networks slow and implementation on wearable devices challenging. To overcome these limitations, spiking neural networks (SNNs) have been applied. SNNs are biologically inspired, event-driven neural networks that compute and transfer information using discrete spikes, which require fewer operations and less complex hardware resources. Thus, they are more energy-efficient compared to other artificial neural networks algorithms.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.6
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• pp.1620-1634
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• 2023

This paper studies the task of embedding nodes with multiple graphs representing multiple information channels, which is useful in a large volume of network clustering tasks. By learning a node using multiple graphs, various characteristics of the node can be represented and embedded stably. Existing studies using multi-channel networks have been conducted by integrating heterogeneous graphs or limiting common nodes appearing in multiple graphs to have similar embeddings. Although these methods effectively represent nodes, it also has limitations by assuming that all networks provide the same amount of information. This paper proposes a method to overcome these limitations; The proposed method gives different weights according to the source graph when embedding nodes; the characteristics of the graph with more important information can be reflected more in the node. To this end, a novel method incorporating a multi-channel gate layer is proposed to weigh more important channels and ignore unnecessary data to embed a node with multiple graphs. Empirical experiments demonstrate the effectiveness of the proposed multi-channel-based embedding methods.