• 센서학회지
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• 제32권6호
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• Journal of electromagnetic engineering and science
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• 제16권1호
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• pp.57-65
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• 2016

In this paper, based on the mode analysis of four-conductor lines, the extended mixed-mode chain-parameters and S-parameters of four-conductor lines are estimated using current division factors. The extended mixed-mode chain-parameters of cascaded four-conductor lines are then obtained with mode conversion. And, the extended mixed-mode S-parameters of cascaded four-conductor lines can be predicted from the transformation of the extended chain-parameters. Compared to the extended mixed-mode S-parameters of four-conductor lines, the cross-mode S-parameters are induced in the extended mixed-mode S-parameters of cascaded four-conductor lines, due to the imbalanced current division factors of cascaded two sections. The generated cross-mode S-parameters make the equivalent different- and common-mode conductors not independent from each other again. In addition, a new mode conversion, which applies the imbalanced current division factors, between the extended mixed-mode S-parameters and standard S-parameters is also proposed in this paper. Finally, the validity of the proposed extended mixed-mode S-parameters and mode conversion is confirmed by a comparison of the simulated and estimated results of shielded cable.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1053-1056
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• 2003

A distortion suppression technology for employing multiple inputs in 3n+1 type current mode Max circuit is proposed using the adjustment of transconductance. If the number of inputs in current mode Max circuit increases, the high frequency distortion in the output signal grows. In this paper, it has been disclosed that the distortion in the multiple input Max circuit is proportional to sum of parasitic capacitance in input terminals, to the derivative of the output signal and also to the inverse of transconductance of the common diode-connected transistor. The proposed idea is by employing as larger transconductance of the common diode-connected transistor as possible. The effectiveness of the proposed idea has been proved through the HSPICE simulation.

• 전력전자학회논문지
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• 제24권1호
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• pp.56-61
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• 2019

In this study, a reduction method of leakage current in a three-level photovoltaic power-conditioning system (PCS) is proposed and verified by simulation and experiment. Leakage current generation is analyzed through an equivalent model of the common mode voltage considering a significant parasitic capacitance existing between the photovoltaic array and ground. A leakage current reduction method using pulse-width modulation (PWM) method is also proposed, and a 10-kW three-level photovoltaic PCS simulation and experiment is performed with a $1{\mu}F$ parasitic capacitor based on 100 nF/kW. The proposed method using the PWM method is verified to reduce the leakage current by 73% compared with the conventional PWM method.

• 전력전자학회논문지
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• 제19권6호
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• 대한전자공학회논문지SD
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• 제40권11호
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• pp.37-44
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• 2003

다수의 입력을 필요로 하는 전류모드 Max 회로에서 고주파 왜곡을 효과적으로 억제할 수 있는 trans conductance 조정 방법을 제안하였다. Max 회로에 인가되는 입력 신호의 개수가 증가하면, 기생 커패시턴스는 입력 단의 개수에 비례하여 누적되게 된다. 본 연구에서는 Max 회로의 왜곡 신호의 크기가 누적된 기생 커패시턴스와 출력신호의 변화율에 비례하며, 공통 다이오드결선 트랜지스터의 transconductance 값에 반비례하게 됨을 밝혔다. 왜곡 억제를 위한 효과적인 방안으로 공통 다이오드결선 트랜지스터의 transconductance 값을 최소화하는 방안을 제시하였다. 이 방법의 효용성은 다양한 수의 입력 신호를 갖는 전류모드 Max 회로에 대해서 HSPICE 시뮬레이션을 통해 입증하였다.

• Journal of Power Electronics
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• 제19권3호
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 추계학술대회
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• pp.96-97
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• 2019

Pulse Width Modulation (PWM) is a widely adopted technique to drive the motor using the voltage source inverters. Since they generate high frequency Common Mode (CM) Voltage, a high shaft voltage in induction motor is induced which leads to parasitic capacitive currents causing adverse effects such as premature deterioration of ball bearings and high levels of electromagnetic emissions. This paper presents an Active Cancellation Circuit (ACC) which can significantly reduce the CM voltage hence the common mode current in the three phase induction motor drives. In the proposed method the CM voltage is detected by the capacitors and applied to the frame of the motor to cancel the CM voltage hence the CM current. Unlike the conventional methods the proposed method does not insert the transformer in between the inverter and motor, a high power rating three phase transformer is not required and no losses associated with it. In addition the proposed method is applicable to any kind of PWM motor drives regardless of their PWM methods. The effectiveness of the proposed method is proved by the experiments with a three phase induction motor (1.1kW 415V/60Hz) combined with a three phase voltage source inverter modulated by the Space Vector Modulation (SVM).

• 대한전자공학회논문지
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• 제4권4호
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• pp.2-12
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• 1967

MOS 전계효과 transistor를 이용하여 직류착동증폭기를 설계하여 A 정도의 극미소직류전류를 측정하는 장치에 관한 연구이다. 등가회로를 이용하여 전압이득과 동상전압변별비를 주는 식을 유도하였으며 유효등가 source 저항을 대단히 높이기 위한 정전류원회로의 실현을 위한 해석을 하였다. 전압이득은 6.6, 상온에서의 drift는 하루에 1.5mv 정도이고 동상전압변별비는 최고 84db 이었다. 이것은 MOS transistor의 대단히 높은 입력저항의 특징을 살려 전잡상등에서 나오는 극미소직류전류의 측정을 간단하게 할 수 있게 하는 것이다.

• 전력전자학회논문지
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• 제23권5호
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• pp.336-344
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• 2018

This study proposes a new PWM method for leakage current reduction and neutral point (NP) current control in three-phase three-level converter employed in bipolar DC distribution systems. The proposed PWM method uses medium vectors only when there is no need to control the NP current. Thus, common mode voltages are held constant to realize zero leakage current. Some space vectors that produce low-frequency common mode voltages are employed to minimize leakage currents when the average NP current needs to be a positive or negative value. The proposed space vector PWM is implemented based on barycentric coordinate. The validity of the proposed PWM method is verified by simulations and experiments.