• Journal of architectural history
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• v.18 no.5
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• pp.81-100
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• 2009

The study on Buddhism architecture in early Joseon dynasty was inactive. The period of King Sejo is important for studying the trend of Buddhism architecture in early Joseon, that was transmitted from the end of Goryeo dynasty, but it was difficult to know its exact situation due to lack of related records. The records were all written by Kim Su-ohn, which are Wongaksabi' 'Sangwonsajungchanggi' 'Bongseonsagi 'Geonginsajungchanggi'. The main hall was mainly second floor and there were necessarily annexed buildings at the right and left of the main hall. So the plane figure of $\Box\Box\Box$ was shown. It was a main stream for main hall. This layout may be referred to search for the origin of the layout in courtyard based structure(中庭形) in the late Joseon dynasty. Most of temples had 3 gates. Some part of horizontal corridor was used as 2 gates and the outer gate, far from main hall, was without corridor. The gate leading to front yard of main hall was called front gate, the next middle gate and the outer gate was Oisamun(外沙門) or Samun(沙門). Im most of the temples, people could enter into the front yard through pavilion which had the function of bell tower. The pavilions were located between front gate and first corridor. It is thought that this layout of the place for making bean curd outside the temple area will contribute to different studies on temples making bean cure in the future. The records about temples's foundation studied above are a little different between temples, but have more similarities. There common denominators represent the architecture tendency of Buddhist temples in the related period. It is thought that such a tendency was also shown on architecture of other temples during the reign of King Sejo as well as Buddhist temples.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.241-244
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• 2012

In this paper, three types of optical receivers are designed using a $0.35-{\mu}m$ standard CMOS technology for plastic optical fiber (POF) applications. Basic common-source transimpedance amplifier (CS-TIA), common-gate TIA (CG-TIA), and regulated-cascode TIA (RGC-TIA) are optimally designed, and their transimpedance gain (TZ gain), 3-dB bandwidth, and noise characteristics are compared and analyzed. As a result of simulations, the RGC-TIA indicates better TZ gain and 3-dB bandwidth than other topologies, and CS-TIA has the best noise performance. Each optical receiver occupies area of $0.35mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.84-92
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• 2000

A GaAs MESFET MMIC transmitter for 2.4 GHz wireless local loop handset is designed and fabricated. The transmitter consists of a double balanced active mixer and a two stage driver amplifier with voltage negative feedback. In particular, a pair of CS-CG(common source-common gate) structure compensates the reduction in dynamic range caused by unbalanced complementary IF input signals. And to suppress the leakage local power at RF port, the mixer is designed by using phase characteristic between the ports of MESFET. At the bias condition of 2.7 V and 55.2 mA, the fabricated MMIC transmitter with chip dimensions of $0.75\times1.75 mm^2$ obtains a measured conversion gain of 38.6 dB, output $P_{idB}$ of 11.6 dBm, and IMD3 at -5 dBm RF output power of -31.3 dBc. This transmitter is well suited for WLL handset.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.261-264
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• 2005

This paper presents the design of a down-conversion mixer with built-in active balun integrated in a $0.25\;{\mu}m$ pHEMT process. The active balun consists of series-connected common-gate FET and common-source FET. The designed balun achieved broadband characteristics by optimizing gate-width and bias condition for the reduction in parasitic effect. From DC to more than 6GHz, the active balun shows the phase error of less than 3 degree and the gain error of less than 0.4 dB. A single-balanced down-conversion mixer with built-in broadband active balun has been designed with optimum width, load resistor and bias for conversion gain and without any matching component for broadband operating. The designed mixer whose size of including on-chip bias circuit is $1\;mm{\times}1\;mm$ shows the conversion gain of better than 7 dB from 2 GHz to 6 GHz and $P_{1dB}$ of -10 dBm at 5.8 GHz

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.53-57
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• 2017

This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.84-87
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• 2000

In this paper, a high gain-broad bandwidth MMIC distributed amplifier was designed using cascaded single section distributed amplifier configuration. The PHEMT for this studies was fabricated at our lab The PHEMT has a 0.2 $\mu\textrm{m}$ gate length. a 80 $\mu\textrm{m}$ unit gate width and 4 gate fingers. A designed MMIC amplifier have higher S$\sub$21/ gain than the common distributed amplifier using the same number of active devices. From the simulated result, we obtained that the S$\sub$21/ gain of DC ∼ 20 GHz bandwidth was 15.6 dB and flatness was ${\pm}$0.9 dB, and input and output reflection coefficient were lower than -8 dB. The simulated gain shows an improvement 7.3 dB compared with those of conventional distributed amplifier. And the chip size is 2.0 ${\times}$ 1.2 $\textrm{mm}^2$.

• The Journal of Korean Medicine
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• v.17 no.2 s.32
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• pp.88-99
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• 1996

Impotence is defined as a consistent inability to achieve or maintain penile erection that is adequate for completion of sexual intercourse. In oriental midicine, the chief cause of impotence is the decline of the fire from the gate of life, and in western medicine that is psycogenic and organic. Because of the increase aging people and psycologic stress that modern people get, impotence became common. This bibliographic study on impotence in the oriental and western medicine books has come to the following conclusions. 1. The main cause of impotence in the oriental medicine is the decline of the fire from the gate of life(命門火衰), followed by the deficiency of both heart and spleen(心脾兩虛), the depression of Liver energy(肝氣鬱結), and attack of blended wetness and heat to the lower wanner(濕熱下注). 2. The theraphics of impotence in oriental medicine are warming and strenghthening Kidney. softness of Liver energy, tonifying the Kidney to relieve mental strain, clear away the wetness-heat, and infairment of Heart and Spleen. 3. The prescriptions of impotence are Yugyeyum, Gyibitang, Soyosan, Sunjitang, and Yongdamsagantang. 4. In the western medicine, psycotherapy, medical therapy and surgical therapy are the major way to treat impotence.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.6
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• pp.16-24
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• 1974

In this paper the method of constructing short and open stable voltage inversion negative immittance converter (VNIC) circuits is proposed according to simplified equivalent models witch consist of a parameter control circuit, and a voltage or a current control circuit. VNIC characteristics can be obtained as gate voltage of common gate connection is controlled by the output of the parameter control circuit corresponding to its input. Constructed circuits are analysed, and the experimental results are compared and cheeked with the calculated results. Errors are found less than 11%. Oscillation behavior of constructed VNIC oscillator is compared with that of negative resistance oscillator.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.