• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
• /
• pp.43-44
• /
• 2006

We have studied electro-optical characteristics and stability of liquid crystal director depending on electrode patterning of common electrode on top substrate in patterned vertical alignment (PVA) mode. In the present studies, new type of common electrode pattern was suggested to enhance a dark state by reducing interference area due to data signal. According to the simulation result, PVA device with new common electrode pattern contributed to Improvement of an aperture ratio.

• 전자공학회논문지D
• /
• 제35D권7호
• /
• pp.32-39
• /
• 1998

This paper presents the experimental results on the 3-electrode DC-PDP which has a common electrode to improve the PDP life cycle. The measured DC characteristic proves the effectiveness of common electrode absorbing about half of discharge currents. The waveforms for pulse memory operation of3-electrode PDP without crosstalk could also be determined from the I-V characteristics. The pulse memory drives of 8*8 cell array show the frequency response fo memory margin and the luminance efficiency of 3-electrode PDP are quite different from genrally known characteristics of 2-electrode DC-PDP.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
• /
• pp.481-484
• /
• 2008

In order to reduce IR drop through common electrode in AMOLED, we propose a novel method to form electrical contact between highly-conductive bus lines and common electrode by using a plasma-assisted patterning of OLED layers and double deposition of the common electrode. Plasma-assisted patterning effects on OLED performance and degradation have been investigated. This patterning method caused turn-on voltage decrease, current flow increase at the same applied OLED voltages, quantum efficiency decrease, and rapid degradation at early stage during the lifetime test. However, comparable 70% luminance lifetime were obtained for both patterned and non-patterned OLEDs.

• 전자공학회논문지B
• /
• 제32B권11호
• /
• pp.1374-1382
• /
• 1995

In TFT-LCDs, as the display size area becomes larger, and the resolution higher, we have to consider the image degradation effects due to the incorporation of the TFT-LCD parameters such as the data-line resistance, the common electrode resistance, the data-line to common parasitic capacitance, and the output characteristics of driver ICs. One of the degradation effects is crosstalk resulting from the coupling between the source bus-line and common electrode. Since a source signal which represents a large number of display data is supposed to vary frequently, the common signal level is affected through the coupling effect, resulting in the degradation of nearby pixel drive signals. Therefore, we proposed a method to compensate for this source-common electrode coupling effect, we also designed and experimented the feasibility of our crosstalk compensation circuit in the actual TFT-LCD. We saw that the newly designed compensation circuit greatly reduced the crosstalk in display pattern image.

• 융합신호처리학회논문지
• /
• 제13권4호
• /
• pp.201-206
• /
• 2012

간접접촉 심전도 측정(Indirect-Contact ECG)은 일상생활에서의 무구속 무자각 측정에 적합한 심전도 측정 방법이다. 본 연구는, 간접접촉 심전도 측정에서 크게 관측되는 60Hz 전원선 잡음을 줄이기 위한 새로운 방법으로, 공통모드 구동 차폐 방식을 제안하였다. 공통 모드 구동 차폐 방식은, 간접 접촉 심전도에서 사용되는 용량성 결합 능동 전극(Capacitive coupling active electrode)을 둘러싼 전기적 차폐(electric shield)의 전압을 공통 모드 전압과 동일하게 유지하는 방법이다. 이 방법은 공통모드 전압의 크기는 그대로 유지하지만, 의복 임피던스 차에 의한 공통모드 전압의 차동 모드 전환에 의한 잡음은 효과적으로 줄일 수 있다. 따라서 두 전극 사이의 의복의 임피던스 차이가 커서 공통 모드 전원 잡음이 심각한 간접 접촉 심전도 측정에서, 효과적으로 공통 모드 잡음을 줄일 수 있다. 실제 간접 접촉 심전도 측정에 제안된 방법을 적용한 결과로 이론적 예상보다는 60Hz 잡음 감소비가 적었지만, 60Hz 잡음이 크게 줄어드는 것을 확인할 수 있었다. 특히 의복 임피던스 차가 크게 발생하는 경우, 예상대로 잡음 감소비가 커짐을 볼 수 있었다. 제안된 방법은 접지 특성이 좋지 않은 측정 조건에서 전원 잡음을 줄이는데 유용할 것으로 기대된다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
• /
• pp.165-168
• /
• 2000

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color fiat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. In addition, PDAST can estimate voltage distributions in common electrode which can affect pixel voltage and feed-through voltage. Since PDAST can simulate the gate, data and the pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of common electrode voltage can be effectively analyzed. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 센서학회지
• /
• 제32권6호
• /
• pp.432-440
• /
• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• 한국전기화학회:학술대회논문집
• /
• 한국전기화학회 2001년도 춘계총회 및 학술발표회
• /
• pp.33-33
• /
• 2001

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
• /
• pp.1258-1261
• /
• 2005

The ramp type bias voltage applied to the common electrode during a reset-period is newly proposed to lower the background luminance and to improve the address discharge characteristics in AC-PDP. The positive ramp bias voltage is applied during the ramp-up period, whereas the negative ramp bias voltage is applied during the ramp-down period. The effects of the voltage slopes in both the positive and negative ramp bias voltages on the background luminance and address voltage characteristics are examined intensively. It is observed that the optimized positive and negative ramp bias voltages applied to the common electrode during the ramp-period can lower the background luminance and also enhance the address discharge characteristics of the AC-PDP.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.148-150
• /
• 2009

We have developed 15 inch, 130 blocks local dimming FEL using printed CNT emitters, in which multiple FE blocks were built with a common gate electrode. Cathode electrode formed by the double-metal technique, in which an insulator is interposed between the addressing bus and cathode electrode.