• 한국전산유체공학회지
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• 제21권4호
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• pp.71-77
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• 2016

The CUPID code is a transient, three-dimensional, two-fluid, thermal-hydraulic code designed for a component-scale analysis of nuclear reactor components. The primary objective of this study is to assess the applicability of CUPID to single-phase turbulent flow analyses of $2{\times}2$ rod bundle subchannel. The bulk velocity at the inlet varies from 1.0 m/s up to 2.0 m/s which is equivalent to the fully turbulent flow with the range of Re=12,500 to 25,000. Adiabatic single-phase flow is assumed. The velocity profile at the exit region is quantitatively compared with both experimental measurement and commercial CFD tool. Three different boundary conditions are simulated and quantitatively compared each other. The calculation results of CUPID code shows a good agreement with the experimental data. It is concluded that the CUPID code has capability to reproduce the turbulent flow behavior for the $2{\times}2$ rod bundle geometry.

• 대한전자공학회논문지TE
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• 제39권4호
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• pp.403-408
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• 2002

본 논문에서는 나카가미-m 확률밀도함수를 이용하여 페이딩 환경을 고려한 DS/CDMA(Direct Sequence Code Division Multiple Access) 시스템의 PN 부호 획득(acquisition)에 대한 성능을 분석하였다. 성능 분석은 PN 부호 획득 시간에 영향을 미치는 검출확률( P/sub D/ : detection probability)과 오경보확률(P/sub FA/ : false alarm probability) 에 대한 식을 유도하여 시물레이션으로 입증하였다. 그 결과 위상 오류를 보정하기 위하여 PLL의 이득을 높이고 레이크 수신기를 동시에 적용할 경우 PN 부호의 검출확률(P/sub D/)은 개선되었고, 오경보확률(P/sub FA/)은 감소하여 PN 부호의 동기 획득 성능을 개선시킬 수 있음을 입증하였다.

• Nuclear Engineering and Technology
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• 제52권10호
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• pp.2274-2284
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• 2020

The Nuclear Fuel Cycle Code "ANICCA" has been developed by SCK•CEN to answer particular questions about the Belgian nuclear fleet. However, the wide range of capabilities of the code make it also useful for international or regional studies that include advanced technologies and strategies of cycle. This paper shows the main features of the code and the facilities that can be simulated. Additionally, a comparison between several codes and ANICCA has also been made to verify the performance of the code by means of a simulation proposed in the last NEA (OECD) Benchmark Study. Finally, a case study of the Belgian nuclear fuel cycle phase out has been carried out to show the possible impact of the transmutation of the minor actinides on the nuclear waste by the use of an Accelerator Driven System also known as ADS. Results show that ANICCA accomplishes its main purpose of simulating the scenarios giving similar outcomes to other codes. Regarding the case study, results show a reduction of more than 60% of minor actinides in the Belgian nuclear cycle when using an ADS, reducing significantly the radiotoxicity and decay heat of the high-level waste and facilitating its management.

• 대한전자공학회논문지TC
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• 제43권12호
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• pp.1-8
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• 2006

본 논문은 유럽의 디지털 방송 규격인 DVB(Digital Video Broadcast)의 업 링크 채널 규격인 DVB-RCS에서 사용되는 터보부호의 특성을 이용하여 반송파의 위상을 추정하는 기법을 제안한다. 위상 추정기는 위치에 따라 크게 외부 단일 추정기와 내부 복수 추정기로 나누었고, 외부 추정 방식은 ML(Maximum Likelihood)과 LMS(Least Mean Square)을 이용하였으며 복수 추정기의 경우에는 LMS(Least Mean Square)와 PSP(Per Survivor Processing)방식 적용하였다. 단일 추정기의 경우 3가지 다른 APP(A Posteriori Probability)알고리즘의 성능을 비교하였으며 단일 추정기와 복수 추정기사이의 성능을 AWGN채널에서 위상오차와 위상잡음(Winner process)이 더해진 모델에서 비교하였다. 복수 추정기의 경우 향상된 2가지 알고리즘을 제안한다. 첫째는 Forward-Backward(Bi-directional)방식의 채널추정기법이고 둘째는 Forward 채널추정 값과 Backward 채널추정 값의 차이의 정보를 이용하는 Binding기법이다.

• 에너지공학
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• 제17권4호
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• pp.218-226
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• 2008

가압 경수로의 주요 기기에서 발생할 수 있는 과도 2상 유동(Two-phase flow) 현상에 대한 해석을 수행하기 위해 원자로 기기 열수력 해석 코드를 개발 중에 있다. 개발중인 기기 열수력 해석 코드는 지배 방정식으로 Two-phase, three-field model을 사용하고 있으며, 복잡한 기하학적 형상의 원자로 기기를 모사하기 위해 비정렬 격자계(Unstructured grid)를 활용하고 있다. 수치해석 기법으로는, 원자로 계통 해석코드 REIAP5가 사용 중이며 대부분의 원자로 내 2상 유동 조건에서 안정적이며 정확하다고 알려진 Semi-implicit 방법을 적용하였다. 그러나 기존의 Semi-implicit 방법은 1차원, 엇갈림격자(Staggered grid)에 대해 개발되었기 때문에 이를 다차원, 비정렬, 비엇갈림 격자(Non-staggered grid)에 적용하기 위해 기존의 Semi-implicit 방법을 수정하였다. 본 논문에서는 수정된 Semi-implicit 방법을 소개하고 이를 이용해 수행한 예비 계산결과를 수록하였다.

• Current Optics and Photonics
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• 제3권6호
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• pp.531-540
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• 2019

Spectral Amplitude Coding Optical Code Division Multiple Access (SAC OCDMA) is an advanced technique in asynchronous environments. This paper proposes design and implementation of a novel quantum logic gate (QLG) code, with code construction algorithm generated without following any code mapping procedures for SAC system. The proposed code has a unitary matrices property with maximum overlap of one chip for various clients and no overlaps in spectra for the rest of the subscribers. Results indicate that a single algorithm produces the same length increment for codes with weight greater than two and follows the same signal to noise ratio (SNR) and bit error rate (BER) calculations for a higher number of users. This paper further examines the performance of a QLG code based SAC-OCDMA system with NAND and direct detection techniques. BER analysis was carried out for the proposed code and results were compared with existing MDW, RD and GMP codes. We demonstrate that the QLG code based system performs better in terms of cardinality, which is followed by improved BER. Numerical analysis reveals that for error free transmission (10^-9), the suggested code supports approximately 170 users with code weight 4. Our results also conclude that the proposed code provides improvement in the code construction, cross-correlation and minimization of noises.

• 전자공학회논문지S
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• 제36S권9호
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• pp.27-35
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• 1999

본 논문은 정수론에 기반하여, PN (Pseudo Noise) 확산부호를 포함한 이원부호의 위상오프셋 오류검출방법을 제안한다. 부호분할다원접속 (code division multiple access : CDMA) 이동 통신 시스템에서는 확산부호의 위상오프셋을 인용하여, 각 기지국을 구분하고 있으므로 위상오프셋을 안다는 것은 매우 중요하다. 부호의 주기가 길지 않을 경우는 한 부호와 이전된 부호 사이의 위상 오프셋은 두 부호를 비교하여 구할 수 있지만, 부호의 주기가 길어지면 이러한 방법으로는 어려움이 따른다. 제안된 방법의 오류검출실패확률 식을 유도하고 시뮬레이션 결과를 이용하여 검증한다. 그리고 회고 구현 방법에 관하여서도 논하며, 간단한 회로로 구현할 수 있음을 보인다.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2007년도 추계 학술대회논문집
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• pp.214-219
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• 2007

Both the bubble rising in a fully filled container and the droplet splash are simulated by a solution code(PowerCFD). This code employs an unstructured cell-centered method based on a conservative pressure-based finite-volume method with interface capturing method (CICSAM) in a volume of fluid(VOF) scheme for phase interface capturing. The present results are compared with other numerical solutions found in the literature. It is found that the present code simulate complex free surface flows such as multi phase flows due to large density difference efficiently and accurately.

• International Journal of Naval Architecture and Ocean Engineering
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• 제4권3호
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• pp.256-266
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• 2012

Cavitating flow simulation is of practical importance for many engineering systems, such as marine propellers, pump impellers, nozzles, torpedoes, etc. The present work has developed the base code to solve the cavitating flows past the axisymmetric bodies with several forebody shapes. The governing equation is the Navier-Stokes equation based on homogeneous mixture model. The momentum is in the mixture phase while the continuity equation is solved in liquid and vapor phase, separately. The solver employs an implicit preconditioning algorithm in curvilinear coordinates. The computations have been carried out for the cylinders with hemispherical, 1-caliber, and 0-caliber forebody and, then, compared with experiments and other numerical results. Fairly good agreements with experiments and numerical results have been achieved. It has been concluded that the present numerical code has successfully accounted for the cavitating flows past axisymmetric bodies. The present code has also shown the capability to simulate ventilated cavitation.

• 한국정보통신학회논문지
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• 제1권2호
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.