• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1654-1665
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• 2008

This paper presents bit splitting methods to apply multilevel modulation to iterative codes such as turbo code, low density parity check code and turbo product code. Log-likelihood ratio method splits multilevel symbols to soft decision symbols using the received in-phase and quadrature component based on Gaussian approximation. However it is too complicate to calculate and to implement hardware due to exponential and logarithm calculation. Therefore this paper presents Euclidean, MAX, sector and center focusing method to reduce the high complexity of LLR method. Also, this paper proposes optimal soft symbol split method for three kind of iterative codes. Futhermore, 16-APSK modulator method with double ring structure for applying DVB-S2 system and 16-QAM modulator method with lattice structure for T-DMB system are also analyzed.

• International conference on construction engineering and project management
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• 2009.05a
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• pp.316-322
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• 2009

The more repetitive, complex and objective the work, the more effective automation is. Code checking is an example of this. Checking building codes through a thick set of drawings is error-prone and time-consuming. In order to overcome this problem, several organizations have initiated efforts to automate building-code checking. Initiated study mainly focused on checking codes for invalidation, required size and crash, and then area of checkable codes have been expanding. But, it has not been considered for codes regarding anti-disaster/egress, which is also issued these days. This study is about how to automatically check codes for anti-disaster and egress based on Korea building codes. The codes can be categorized as five sections: egress way, material/capability, principals of evacuation, evacuation stairway and fire protection partition. To check automatically, there are problems, such as expression of codes for egress and limitation of extractable information from the BIM model. This paper shows what problems exist and assignments to be resolved. Also, current developing processes are presented, and suggestions are made about the direction for the work that remains.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.8
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• pp.3749-3768
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• 2018

As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.299-304
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• 2008

For perpendicular magnetic recording channels, it is hard to expect improving the performance by using the PRML or NPML. Hence, we exploit LDPC code to improve the performance. In this paper, we examine a single message-passing detector/decoder matched to the combination of a perpendicular magnetic recording channel detector and an LDPC code decoder. We examine the performance of channel iteration with joint LDPC code on perpendicular magnetic recording channel, and simplify the complexity of the message-passing detector algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.175-180
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• 2009

When we apply the LDPC code for high density optical storage channel, it is necessary to make an algorithm that the modulation code decoder must feed the LDPC decoder soft-valued information because LDPC decoder exploits soft values using the soft input. Therefore, we propose the soft-input soft-output run-length limited 17PP decoding algorithm and compare performance of LDPC codes. Consequently, we found that the proposed soft-input soft-output decoding algorithm using 17PP is 0.8dB better than the soft-input soft-output decoding algorithm using (1, 7) RLL.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.17-21
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• 2017

Since holographic data storage has the advantage of high recording density and data transfer rate, it is a candidate for the next generation storage systems. However, Holographic data storage system is affected by interpage interference and two dimensional intersymbol interference. Also, burst error occurs by physical impact. In this paper, we propose an LDPC product code using modified log-likelihood ratio and extrinsic information to correct burst error and improve performance of holographic data storage. The performance of proposed LDPC product code is 0.5dB better than that of the conventional LDPC code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.