• Title/Summary/Keyword: CoDisplay

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Development of Dry-Vacuum-Pump for Semiconductor/Display Process (반도체/디스플레이 공정급 건식진공펌프 개발 개요)

  • Lee, S.Y.;Noh, M.;Kim, B.O.;Lee, A.S.
    • Journal of the Korean Vacuum Society
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    • v.19 no.4
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    • pp.265-274
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    • 2010
  • The excellent performance and stability of dry-vacuum-pump is essential to create and maintain high quality vacuum condition in semiconductor and display process. The development of dry-vacuum-pump needs systematic consideration for target application as well as delicate mechanical issues. Here, we introduce a development procedures of dry-vacuum-pump for semiconductor-process-class.

Preparation of Charged Composite Particles for Electrophoretic Display (전기영동 디스플레이용 대전 복합입자의 제조)

  • Na, Hae-Jin;Baek, Jeong-Ju;Kim, Ji-Suk;Kim, Sung-Soo
    • Polymer(Korea)
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    • v.33 no.4
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    • pp.347-352
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    • 2009
  • Charged organic-inorganic composite particles were prepared for the application to electrophoretic display technology such as electronic paper. $TiO_2$ and $Co_3O_4$ particles were used for core particles and were coated with poly(methyl methacrylate) by dispersion polymerization. Composite particles were endowed with charge moiety for electrophoresis; positive charge for $TiO_2$ and negative charge for $Co_3O_4$ composite particles. Scanning electron microscopic results revealed that the charged composite particles have spherical shape. Densities of the composite particles were controlled to be that of medium of electrophoresis. Density of $TiO_2$ particle changed from 4.02 to 1.44 g/$cm^3$ after the polymer coating, and that of $Co_3O_4$ particles changed from 6.11 to 1.49 g/$cm^3$. Urea, melamine, and formaldehyde were used as wall materials for capsule, and microcapsule containing black or white particles inside were prepared by in-situ polymerization. Microcapsule showed the inspection by a video microscope demonstrated the formation of uniform transparent capsules.

Modified Ramp-Reset Waveform Robust for Variable Panel Temperature and its Discharge Characteristics

  • Jang, Soo-Kwang;Tae, Heung-Sik;Kim, Soon-Bae;Jung, Eun-Young;Suh, Kwang-Jong;Ahn, Jung-Chull;Heo, Eun-Gi;Lee, Byung-Hak;Lee, Kwang-Sik
    • Journal of Information Display
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    • v.7 no.1
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    • pp.25-29
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    • 2006
  • By the voltage threshold (Vt) close-curve measurement method, the changes in the discharge characteristics such as a firing voltage and IR emission among the three electrodes were examined relative to the low or high panel temperature ranging from -10 to $80^{\circ}$. The variation in the panel temperature was found significantly influence the surface discharge between the MgO surfaces rather than the plate gap discharge between the MgO and phosphor layers. Based on this experimental observation, a modified reset waveform that alleviates the surface discharge during a ramp-up and -down period was deeloped. By adopting the proposed reset waveform, a stable address discharge could be obtained irrespective of the panel temperature variation.

Effects of some factors on the thermal-dissipation characteristics of high-power LED packages

  • Ji, Peng Fei;Moon, Cheol-Hee
    • Journal of Information Display
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    • v.13 no.1
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    • pp.1-6
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    • 2012
  • Decreasing the thermal resistance is the critical issue for high-brightness light-emitting diodes. In this paper, the effects of some design factors, such as chip size (24 and 35 mil), substrate material (AlN and high-temperature co-fired ceramic), and die-attach material (Ag epoxy and PbSn solder), on the thermal-dissipation characteristics were investigated. Using the thermal transient method, the temperature sensitivity parameter, $R_{th}$ (thermal resistance), and junction temperature were estimated. The 35-mil chip showed better thermal dissipation, leading to lower thermal resistance and lower junction temperature, owing to its smaller heat source density compared with that of the 24-mil chip. By adopting an AlN substrate and a PbSn solder, which have higher thermal conductivity, the thermal resistance of the 24-mil chip can be decreased and can be made the same as that of the 35-mil chip.

A Link Layer Design for DisplayPort Interface

  • Jin, Hyun-Bae;Yoon, Kwang-Hee;Kim, Tae-Ho;Jang, Ji-Hoon;Song, Byung-Cheol;Kang, Jin-Ku
    • Journal of IKEEE
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    • v.14 no.4
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    • pp.297-304
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    • 2010
  • This paper presents a link layer design of DisplayPort interface with a state machine based on packet processing. The DisplayPort link layer provides isochronous video/audio transport service, link service, and device service. The merged video, audio main link, and AUX channel controller are implemented with 7,648 LUTs(Loop Up Tables), 6020 register, and 821,760 of block memory bits synthesized using a FPGA board and it operates at 203.32MHz.

Development of a New Hybrid Silicon Thin-Film Transistor Fabrication Process

  • Cho, Sung-Haeng;Choi, Yong-Mo;Kim, Hyung-Jun;Jeong, Yu-Gwang;Jeong, Chang-Oh;Kim, Shi-Yul
    • Journal of Information Display
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    • v.10 no.1
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    • pp.33-36
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    • 2009
  • A new hybrid silicon thin-film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low-temperature poly-Si (LTPS) and a-Si:H TFTs on the same substrate as a backplane of the active-matrix liquid crystal flat-panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the activematrix LCD panel for the gate driver circuit, and a-Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a-Si:H TFT fabrication process in the bottom-gate, back-channel etch-type configuration. The ion-doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of $4\sim5cm^2/V{\cdot}s$ and $0.5cm^2/V{\cdot}s$ for the LTPS and a-Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1" WXGA+(1440$\times$900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a-Si:H TFT gate driver integration circuit

Circuit Integration Technology of Low-Temperature Poly-Si TFT LCDs

  • Motai, Tomonobu
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.75-80
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    • 2004
  • By the SOG (System-on-Glass) technology with excimer laser anneal process, the number of IC chips and the area of the mounted IC chips on the printed circuit board are reduced. In new circuit integrations on the glass substrate, we have developed D/A converter including the new capacitor array, amplifier comprising the original comparators and new display device with capturing images by integrated sensor into a pixel. This paper discusses the application of circuit integration of low-temperature poly-Si.

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Indium Tin Oxide (ITO) Thin Film Fabricated by Indium-Tin-Organic sol with ITO Nanoparticle at Low Temperture

  • Hong, Sung-Jei;Chang, Sang-Gweon;Han, Jeong-In
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.1334-1338
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    • 2006
  • In this work, indium tin oxide (ITO) thin film was fabricated by indium-tin-organic sol including ITO nanoparticle. ITO nanoparticle showed ultrafine size about 5 nm and (222) preferred crystal structure. Also, ITO sol-gel thin film showed good optical transmittance over 83% and electrical resistance less than $7\;{\times}\;10^3\;{\Omega}$.

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A Study on the Direct Bonding Method using the E-Beam Evaporated Silicon dioxide Film (전자선 증착된 실리콘 산화막층을 이용한 직접 접합에 관한 연구)

  • Park, Heung-Woo;Ju, Byeong-Kwon;Lee, Yun-Hi;Jeong, Seong-Jae;Lee, Nam-Yang;Koh, Ken-Ha;Haskard, M.R.;Park, Jung-Ho;Oh, Myung-Hwan
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1988-1990
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    • 1996
  • In this work, we have grown or evaporated thermal oxide and E-beam oxide on the (100) oriented n-type silicon wafers, respectively and they were directly bonded with another silicon wafer after hydrophilization using solutions of three types of $HNO_3$, $H_{2}SO_{4}$ and $NH_{4}OH$. Changes of average surface roughness after hydrophilizations of the single crystalline silicon wafer, thermal oxide and E-beam evaporated silicon oxide were studied using atomic force microscope. Bonding interfaces of the bonded pairs were inspected using scanning electron microscope. Void and non-contact area of the bonded pairs were also inspected using infrared transmission microscope.

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Experimental Analysis on the Anodic Bonding with Evaporated Glass Layer

  • Choi, Woo-Beom;Ju, Byeong-Kwon;Lee, Yun-Hi;Jeong, Seong-Jae;Lee, Nam-Yang;Koh, Ken-Ha;Haskard, M.R.;Sung, Man-Young;Oh, Myung-Hwan
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1946-1949
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    • 1996
  • We have performed silicon-to-silicon anodic bonding using glass layer deposited by electron beam evaporation. Wafers can be bonded at $135^{\circ}C$ with an applied voltage of $35V_{DC}$, which enables application of this technique to the vacuum packaging of microelectronic devices, because its bonding temperature and voltage are low. From the experimental results, we have found that the evaporated glass layer more than $1\;{\mu}$ m thick was suitable for anodic bonding. The role of sodium ions for anodic bonding was also investigated by theoretical bonding mechanism and experimental inspection.

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