• Title/Summary/Keyword: CoDisplay

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Tactile Transfer and Display Method using Data Glove and Vibration Motors Module (데이터 글로브와 진동모터를 이용한 촉각전달 및 제시 방법)

  • Kang, Hyung-Gu;Choi, Youngjin
    • Journal of Institute of Control, Robotics and Systems
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    • v.19 no.12
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    • pp.1138-1144
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    • 2013
  • This paper proposes a tactile transfer and display method between a data glove and vibration motors module. The data glove is developed to capture the hand postures and to measure the grip forces. The measured data are simplified with the proposed 5-bit transfer and display algorithm, and the vibration motors module is developed to display the measured hand posture and grip force to the operator. The proposed 5-bit algorithm contains both an 8-step hand posture and 4-step grip force level information for tactile transfer to the vibration motors module. Also, the effectiveness of the proposed method is shown through several experiments.

A Load Sharing Method of Parallel-connected Two Interleaved CrM Boost PFC Converters (병렬 연결된 두 개의 Interleaved CrM Boost PFC 컨버터의 부하 공유 방법)

  • Kim, Moon-Young;Kang, Shinho;Kang, Jeong-Il;Han, Jonghee
    • The Transactions of the Korean Institute of Power Electronics
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    • v.26 no.1
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    • pp.53-58
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    • 2021
  • Operation of the interleaved Boost PFC converter in Critical Conduction Mode (CrM) shows the advantages of high efficiency and good EMI characteristics owing to the valley switching of FET. However, when it is designed for a highly pulsating load, operation at a relatively high frequency is inevitable at non-pulsating typical load condition, resulting in efficiency degradation. Moreover, the physical size of the inductor becomes problematic because of the nature of the CrM operation, where the inductor peak current is about two times the inductor average current, thereby requiring high DC-bias characteristics, which is worse when the output power is high. In this study, a new parallel driving method of two sets of interleaved boost PFC converters for highly pulsating high-power application is proposed. The proposed method does not require any additional load-sharing controller, resulting in high efficiency and smaller inductor size.

Low Power Consumption Technology for Mobile Display

  • Lee, Joo-Hyung
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.402-403
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    • 2009
  • A variety of power reduction technologies is introduced and the benefits of the technologies are discussed. PenTile$^{(R)}$ DBLC (Dynamic Brightness LED Control) combined with SABC (Sensor-Based Adaptive Brightness Control) enables to achieve the average LED power consumption to one third. The panel power reduction of 25% can be achieved with low power driving technology, ALS (Active Level Shifter). MIP (Memory In Pixel) is expected to be useful in transflective display because the whole display area can be utilized in reflective mode with power consumption of 1mW.

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Nanoparticle Cleaning of AMLCD Backplane

  • Oh, J.H.;Kang, D.H.;Choi, M.H.;Kim, S.H.;Choo, B.K.;Hur, J.H.;Jang, J.;Kim, I.H.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.1425-1428
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    • 2006
  • We have proposed a novel cleaning technology with organic nanoparticles for high-performance TFT array. The surface of the TFT layer becomes more hydrophilic after cleaning by the nanoparticles. This is concluded from the comparison of contact angles for the samples cleaned by various methods. It is found that the drain currents in the subthreshold and off-state regions are less than those for the TFTs cleaned with conventional method.

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Analysis of the Horizontal Block Mura Defect

  • Mi, Zhang;Jian, Guo;Chunping, Long
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08b
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    • pp.1597-1599
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    • 2007
  • In TFT-LCD, mura is a defect which degrades the display quality. The resistance difference between gate lines is the main cause of H-Block mura. Two methods could eliminate this defect. A thinner gate layer or gate fan-out pattern decrease mura level. H-Block mura has been reduced after implementing the new schemes.

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The Research on Vertical Block Mura in TFT-LCD

  • Long, Chunping;Wang, Wei;Wu, Hongjiang
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.841-844
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    • 2007
  • In this paper, a vertical block mura, which massively occurred in the LCD products, was investigated extensively by various methods, source drain (SD) line shift is found out to be one of the key reasons. This work to some extent, establishes theoretic hypothesis for further research and solutions similar issues.

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Study on Property Variations of $CoSi_2$ Electrode with Its Preparation Methods ($CoSi_2$ 전극 구조의 증착법에 따른 특성 변화 연구)

  • Nam, Hyoung-Gin
    • Journal of the Semiconductor & Display Technology
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    • v.6 no.4
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    • pp.5-9
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    • 2007
  • Phase transition and dopant redistribution during silicidation of $CoSi_2$ thin films were characterized depending on their preparation methods. Our results indicated that cleanness of the substrate surface played an important role in the formation of the final phase. This effect was found to be reduced by addition of W resulting in the formation of $CoSi_2$. However, even in this case, the formation of the final phase was achieved at the cost of extra thermal energy, which induced rough interface between the substrate and the silicide film. As for the dopant redistribution, the deposition sequence of Co and Si on SiGe was observed to induce significant differences in the dopant profiles. It was found that co-deposition of Co and Si resulted in the least redistribution of dopants thus maintaining the original dopant profile.

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Optimal Barrier Coating Processes to maximize the Alignment of Layers on Plastic Substrates

  • Lee, Woo-Jae;Hong, Mun-Pyo;Seo, Jong-Hyun;Rho, Soo-Guy;Hong, Wang-Su;Jeon, Hyung-Il;Kim, Sang-Il;Chung, Kyu-Ha
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.988-990
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    • 2005
  • A 5.0-inch plastic TFT-LCD with the resolution of $400{\times}3{\times}300$ lines (120ppi) was developed. The device is a transmissive type with the transparent PES plastic substrates. The PES films with one side barrier coating were used for the device. In order to produce the high resolution display device, the alignments between all the layers for the TFT and CF are essential. The fundamental shrinkage effect and the thermal expansion behavior of the plastic substrates with and without the barrier coatings were studied. The proper annealing processes followed by immediate second bar-rier coating processes provide the optimal alignment between all the layers of the TFT and CF..

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