• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2081-2086
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• 2015

The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.5
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• pp.116-124
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• 2012

In this paper, we propose an efficient lighting control system design for AVR based LSDM control. This paper, an efficient lighting control system design for LSDM control be design divided as the signal control part for I/O data bus and the timer/counter part for clock signal control according to operating conditions. LSDM control logic be optimization to PORTx and DDRx register by specifying the logical value of each bit for effective control signal processing. And, the LSDM control signal by lighting control program execution of ATmega128 be designed to be LSDM lighting control by control logic operating. In this paper, a proposed lighting control system were measured to power loss rate to proved the power loss reduction about lighting status of LSDM control logic by download the lighting control program to system through serial from host PC. As a measurement result, a proposed lighting control system than the existing lighting control system were proved to be effective to the overall power consumption reduction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.1
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• pp.49-55
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• 2012

Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.862-872
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• 1998

In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the aecurate operation and effectiveness of the proposed architecture.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.227-236
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• 2017

Quantum-dot cellular automata(QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Various circuits on QCA have been researched until these days, a latch required for counter and state control has been proposed as a component of sequential logic circuits. A latch uses a feedback loop to maintain previous state. In QCA, a latch uses a square structure using 4 clocks for feedback loop. Previous latches have been proposed using many cells and clocks in coplanar. In this paper, in order to eliminate these defects, we propose a SR and D latch using multilayer structure on QCA. Proposed three dimensional loop structure is based on multilayer and consists of 3 layers. Each layer has 2 clock differences between layers in order to reduce interference. The proposed latches are analyzed and compared to previous designs.

• Korean Journal of Applied Biomechanics
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• v.17 no.2
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• pp.31-40
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• 2007

Proper weight shifting is essential for a successful shot in golf swing and this could be described by means of the ground forces between the feet and ground. It is assumed that the ground forces would different according to the club used because the length and swing weight of each club is different. But, in present, it is not clear what changes are made by the change of clubs and this affect the swing motion. Therefore this study focused on the investigation of the changes of the ground forces and ground reaction forces (GRF) by the change of club length. The subjects were three professional male golfers. Four swings (driver, iron 3, iron 5, and iron 7) for each subject were taken by two high speed video cameras and two AMTI force platforms were used to measure the GRF simultaneously. Kwon GRF 2.0 and Mathcad 13 software were used to post processing the data. Changes of the three major component of GRF (Vertical, lateral, anterior-posterior force) at 10 predefined events were analyzed including the maximum. Major findings of this study were as follows. 1. Vertical forces; - There were no significant changes until the top of backswing. - Maximum was occurred at the club horizontal position in the downswing for both feet. The shorter club produced more maximum forces than longer ones in the left foot, but reverse were true for the right foot. - Maximum forces at impact shows the same patterns. 2. Lateral forces; Maximum was occurred at the club horizontal position for both feet, but there were no lateral forces because the direction of two forces was different. Maximum force pattern by different clubs was same as the vertical component. 3. Anterior-posterior forces; - This component made a counter-clock wise moment about a vertical axis located between two foot until the club vertical position was reached during the backswing, and reverse moment were produced when the club reached horizontal at the downswing. - Also this component made a forward moment about a horizontal axis located in the CG during the fore half of the downswing, and a reverse moment until the club reached vertical at the follow through phase. Maximum was occurred at the club vertical in the downswing for both feet. The longer club produced more maximum forces than shorter ones for both feet.