• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1004-1009
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• 2004

Precise time synchronization is a main technology in high-speed communications, parallel and distributed processing systems, Internet information industry and electronic commerce. Synchronized clocks are useful for many leasers. Often a distributed system is designed to realize some synchronized behavior, especially in real-time processing in factories, aircraft, space vehicles, and military applications. Nowadays, time synchronization has been compulsory thing as distributed processing and network operations are generalized. A network time server obtains, keeps accurate and precise time by synchronizing its local clock to standard reference time source and distributes time information through standard time synchronization protocol. This paper describes design issues and implementation of a network time server for time synchronization especially based on a clock model. The system uses GPS (Global Positioning System) as a standard reference time source and offers UTC (universal Time coordinated) through NTP (Network Time protocol). Implementation result and performance analysis are also presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• Journal of KIISE:Software and Applications
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• v.37 no.8
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• pp.647-652
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• 2010

Esterel is an imperative synchronous language well-adapted to control-intensive systems. When an Esterel program is translated to a circuit, the synchronizer of a parallel statement may be executed more than once in a clock; the synchronizer is called schizophrenic. Existing compilers cure the problems of schizophrenic parallel synchronizers using logic duplications. This paper proposes the conditions under which a synchronizer causes no problem in circuits when it is executed more than once in a clock. In addition we design a detection algorithm based on those conditions. Our algorithm detects schizophrenic parallel synchronizers that have to be duplicated in Esterel source codes so that compilers can save the size of synthesized circuits

• ETRI Journal
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• v.27 no.6
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• pp.691-696
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• 2005

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very-large-scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a $5{\times}5$ matrix of data cells in a Virtex-E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.680-687
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• 2018

Borehole radar is a radar used for underground resources and geological exploration purposes. It needs a high-speed sampler to transmit electromagnetic waves with a pulse width of several ns and to receive reflected waves of several tens to several hundreds of MHz reflected from the object to be surveyed. ETS (Equivalent-Time Sampling), which can achieve sampling performance of several GHz with a sampling frequency of several tens of MHz, is suitable for use as a sampler of a borehole radar receiver. In this paper, we propose a method to control the sampling clock delay, which is the most important factor in ETS sampler design, using four clocks with phase difference of $90^{\circ}$ for one clock source. The proposed method can reduce the time required to acquire the data within the set interval by 1/25 than the conventional method using the delay generator. When the implemented sampler is applied to the receiver of existing borehole radar, it is possible to accumulate 58 additional times due to the shortened sampling time. In addition, by using one delay control logic compared with the conventional method using several sampling clock delay control logic in order to satisfy the target sampling range, it is possible to omit the correction process which was necessary in the past. As a result, the structure of the system can be simplified and a uniform sampler can be realized.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.24 no.1
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• pp.1-6
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• 1988

For the purpose of making the detection range of fish detection system more longer and computerizing the system a parametric sound source, a timer and a digitizing circuit for the Apple II computer have been studied. The parametric sound of 5 KHz generated by passing AND gate two signals from carrier signal generator of 200KHz with modulator of 5KHz. This parametric acoustic source of 5KHz difference frequency had more higher directional resolution of 10 degrees than single frequency sound of 200KHz. Peripheral interface adaptor MC 6821 was adopted for interfacing to the Apple II personal computer. The timer consisted of six decade binary coded decimal counters (74 LS 190), and the digitizing circuit consisted of a sample and hold (LF 398) and an A/D converter(ADC 0808). The timer with 10KHz clock pulse had the measuring time from 0.1msec to 100sec. This time measuring range was satisfactory for the aim of the fish finding acoustic system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.9
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• pp.4271-4294
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• 2018

Communication cost is the most important factor in Wireless Sensor Networks (WSNs), as exchanging control keying messages consumes a large amount of energy from the constituent sensor nodes. Time-based Dynamic Keying and En-Route Filtering (TICK) can reduce the communication costs by utilizing local time values of the en-route nodes to generate one-time dynamic keys that are used to encrypt reports in a manner that further avoids the regular keying or re-keying of messages. Although TICK is more energy efficient, it employs no re-encryption operation strategy that cannot determine whether a healthy report might be considered as malicious if the clock drift between the source node and the forwarding node is too large. Secure SOurce-BAsed Loose Synchronization (SOBAS) employs a selective encryption en-route in which fixed nodes are selected to re-encrypt the data. Therefore, the selection of encryption nodes is non-adaptive, and the dynamic network conditions (i.e., The residual energy of en-route nodes, hop count, and false positive rate) are also not focused in SOBAS. We propose an energy efficient selection of re-encryption nodes based on fuzzy logic. Simulation results indicate that the proposed method achieves better energy conservation at the en-route nodes along the path when compared to TICK and SOBAS.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.817-824
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• 2016

A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than $10^{-12}$ with $2^7-1$ pseudo-random binary sequence (PRBS) pattern for both signaling directions.

• Journal of the Korea Society for Simulation
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• v.10 no.4
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• pp.21-30
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• 2001

In this paper, EMI measurement, the STGU simulation being conducted, filter design, its characteristics, and its implementation to the PCB, and finally test results are discussed. When the low pass filter was implemented within the STGU, the power of EMI decreased more than 20dBm. Finally, when TE and MTIE, two important quality measure in synchronous reference clock, was assessed, ITU-T G813 requirement was satisfied. EMI(Electromagnetic Interface) is a measure of electomagnetic radiation from equipment in the range of 10KHz to 3GHz, and can cause unexpected reactions of electronics/electrical equipment. In this study, for safe and stable communication operation, a STGU (System Timing Generation Unit), which is a 2.5G SDH System and a major EMI source, was employed to simulate electromagnetic interface. Using Open-Site test, the power of fundamental frequency of EMI of interest and its harmonics were measured. Also, a low pass filter at cut-off frequency of 2GHz was specifically designed for this study to minimize the effect of EMI between electronic components.