• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.417-426
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• 1996

The end-to-end service clock recovery is a critical issue in providing constandt bit rate service through ATM network. The Synchronous Residual Time Stamp(SRTS) algorithm is used to recovery the source clock using time stamp of transmitter. In thispaper, we propose a Differential Residual Time Stamp (DRTS) transmission mechanism to effectively deliver the timing information of source clock in SRTS algorithm. The RTS transmission method simple in its hardware. From the results of field trial of DS3 rate interactive video communication system through B-ISDN testbed, it can be identified that DRTS method is superior to the RTS method.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.220-227
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• 2017

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Journal of IKEEE
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• v.15 no.2
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.

• Interdisciplinary Bio Central
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• v.1 no.1
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• pp.5.1-5.4
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• 2009

This article is an addendum to the authors’ previous article (Kim, J. et al. (2008) Plant Cell 20, 307-319). The instrumentation and software described in this article were used to analyze the circadian leaf movement in the previous article. Here, we provide detailed and practical information on the instrumentation and the software. The source code of the LMA program is freely available from the authors. The circadian clock regulates a wide range of cyclic physiological responses with a 24 hour period in most organisms. Rhythmic leaf movement in plants is a typical robust manifestation of rhythms controlled by the circadian clock and has been used to monitor endogenous circadian clock activity. Here, we introduce a relatively easy, inexpensive, and simple approach for measuring leaf movement circadian rhythms using a USB-based web camera, public domain software and a Leaf Movement Assay (LMA) program. The LMA program is a semi-automated tool that enables the user to measure leaf lengths of individual Arabidopsis seedlings from a set of time-series images and generates a wave-form output for leaf rhythm. This is a useful and convenient tool for monitoring the status of a plant's circadian clock without an expensive commercial instrumentation and software.

• Journal of Positioning, Navigation, and Timing
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• v.3 no.4
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• pp.163-170
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• 2014

A pseudolite is used as a GPS backup system, and is also used for the purpose of indoor navigation and correction information transmission. It is installed on the ground, and transmits signals that are similar to those of a GPS satellite. In addition, in recent years, studies on the improvement of positioning accuracy using the pseudorange measurement of a pseudolite have been performed. As for the effect of the time synchronization error between a pseudolite and a GPS satellite, a time synchronization error of 1 us generally induces a pseudorange error of 300 m; and to achieve meter-level positioning, ns-level time synchronization between a pseudolite and a GPS satellite is required. Therefore, for the operation of a pseudolite, a time synchronization algorithm between a GPS satellite and a pseudolite is essential. In this study, for the time synchronization of a pseudolite, "a pseudolite time synchronization method using the time source of UTC (KRIS)" and "a time synchronization method using a GPS timing receiver" were introduced; and the time synchronization performance depending on the pseudolite time source and reference time source was evaluated by designing a software-based pseudolite time synchronization performance evaluation simulation platform.

• Journal of Information Processing Systems
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• v.16 no.3
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• pp.541-556
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• 2020

Wireless networks have become integral to society as they provide mobility and scalability advantages. However, their disadvantage is that they cannot control the media, which makes them vulnerable to various types of attacks. One example of such attacks is the evil twin access point (AP) attack, in which an authorized AP is impersonated by mimicking its service set identifier (SSID) and media access control (MAC) address. Evil twin APs are a major source of deception in wireless networks, facilitating message forgery and eavesdropping. Hence, it is necessary to detect them rapidly. To this end, numerous methods using clock skew have been proposed for evil twin AP detection. However, clock skew is difficult to calculate precisely because wireless networks are vulnerable to noise. This paper proposes an evil twin AP detection method that uses a multiple-feature-based machine learning classification algorithm. The features used in the proposed method are clock skew, channel, received signal strength, and duration. The results of experiments conducted indicate that the proposed method has an evil twin AP detection accuracy of 100% using the random forest algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.39-45
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• 2011

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.216-223
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• 2005

A computer clock has limits in accuracy and precision affected by its inherent instability, the environment elements, the modification of users, and errors of the system. So the computer clock needs to be synchronized with a standard clock if the computer system requires the precise time processing. The purpose of synchronizing clocks is to provide a global time base throughout a distributed system. Once this time base exists, transactions among members of distributed system can be controlled based on time. This paper discusses the integrated approach to clock synchronization. An embedded system is considered for time synchronization based on the GPS(Global Positioning System) referenced time distribution model. The system uses GPS as standard reference time source and offers UTC(Universal Time Coordinated) through NTP(Network Time Protocol). A clock model is designed and adapted to keep stable time and to provide accurate standard time with precise resolution. Private MIB(Management Information Base) is defined for network management. Implementation results and performance analysis are also presented.