• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.225-233
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• 2004

A novel real-time color gamut mapping method is described. The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for digital TV display quality enhancement. The high definition digital TV display devices operate at the clock speed of around 70MHz ～ 150MHz and permit several nano seconds for real-time gamut mapping. Thus, the concept of three-dimensional reduced resolution look-up table is introduced for real-time processing. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in FPGA and ASIC and also successfully adopted in digital TV display quality enhancement purposes.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1590-1597
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• 2000

This paper describes a CMOS data recovery circuit using oversampling technique. Digital oversampling is done using a delay locked loop circuit locked to multiple clock periods. The delay locked loop circuit generates the vernier delay resolution less than the gate delay of the delay chain. The transition and non-transition counting algorithm for 4x oversampling was implemented for data recovery and verified through FPGA. The chip has been fabricated with 0.6um CMOS technology and measured results are presented.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.106-109
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• 2004

In this project, we have developed the eye-safe LRF system of 1.54 ${\mu}{\textrm}{m}$ wavelength using OPO. The maximum measured distance was 3.7km in outdoor experiment. We used Nd：YAG (1064nm) as a laser medium. It was applied BBO to construct the system. We also developed a time-counter for the range finder using a method of TOF (time of flight). The counter-clock used at the time counter was 320MHz making resolution within $\pm$1m. Start and stop signals were detected by two channel systems using PIN and APD. The LRF's repetition rate was 4 times per minute. The energy was measured to be over 9mJ. And, pulse-duration was 23ns. Resolution was $\pm$2m at the distance measurement using a target.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.47-50
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• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

• Proceedings of the IEEK Conference
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• summer
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• pp.122-127
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• 2004

The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for display quality enhancement. The high definition display devices operate at the clock speed of around $70\;MHz\;\sim\;150\;MHz$ and permit several nano seconds for real-time processing. Thus, the concept of three-dimensional reduced resolution look-up table is used. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in ASIC and also successfully adopted in display quality enhancement purposes.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.361-364
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• 2003

In this paper, a high-resolution multibit sigma-delta modulator implemented in a.0.35-um CMOS technology is introduced. This modulator consists of two switched capacitor integrators, 3-bits A/D converter, and 3-bits D/A converter For the verification of the internal function blocks, HSPICE simulator is used. This circuit is normally operated at 130 MHz clock and the total power dissapation is 70 mW.

• Journal of Positioning, Navigation, and Timing
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• v.10 no.3
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• pp.159-168
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• 2021

Precise Point Positioning-Real Time Kinematic (PPP-RTK) is an improved PPP method that provides the user receiver with satellite code and phase bias correction information in addition to the satellite orbit and clock, thus enabling single-receiver ambiguity resolution. Single station PPP-RTK concept is special case of PPP-RTK in that corrections are computed, instead of a network, by only one single GNSS receiver. This study is performed to experimentally verify the positioning accuracy performance of single baseline RTK level by a user who utilizes correction for a single station PPP-RTK using dual frequencies. As an experimental result, the horizontal and vertical 95% accuracy was 2.2 cm, 4.4 cm, respectively, which verify the same performance as the single baseline RTK.