• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.37-42
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• 2007

Clock grid networks are now common in most high performance microprocessors. This paper presents a new effective modeling and simulation methodology for the clock grid using scattering parameter. It also shows the effect of wire width and grid size on the clock skew of the grid. The interconnection of the clock grid is modeled by RC passive elements. The results show that the error is within 10 % comparing to Hspice simulation results.

• Earthquakes and Structures
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• v.22 no.1
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• pp.65-82
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• 2022

This paper presents a structural performance assessment of a historical masonry clock tower both using numerical and experimental process. The numerical assessment includes developing of finite element model with considering different types of soil-structure interaction systems, identifying the numerical dynamic characteristics, finite element model updating procedure, nonlinear time-history analysis and evaluation of seismic performance level. The experimental study involves determining experimental dynamic characteristics using operational modal analysis test method. Through the numerical and experimental processes, the current structural behavior of the masonry clock tower was evaluated. The first five experimental natural frequencies were obtained within 1.479-9.991 Hz. Maximum difference between numerical and experimental natural frequencies, obtained as 20.26%, was reduced to 4.90% by means of the use of updating procedure. According to the results of the nonlinear time-history analysis, maximum displacement was calculated as 0.213 m. The maximum and minimum principal stresses were calculated as 0.20 MPa and 1.40 MPa. In terms of displacement control, the clock tower showed only controlled damage level during the applied earthquake record.

• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.163-164
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• 2014

Pseudolite systems are used for backup systems of GPS satellite or indoor navigation systems. The pseudolite transmits GPS-like signal on the ground. Fundamentally, to estimate a position, clock synchronization among satellites is essential, because GPS receiver uses measurement based on TOA. Therefore, in order to improve the navigation performance in applications using pseudolite, clock synchronization with GPS satellites is required. This paper proposes design of monitoring system for pseudolite clock synchronization. The monitoring system analyzes clock synchronization accuracy of pseudolite and can be used for clock adjustment.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1157-1160
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• 2003

We proposed a study on optimal clock period selection algorithm for low power RTL design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.1-8
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• 2005

SPEC CPU2000 is an widely used benchmark program, both in industry and in academy, for measuring compute-intensive performance of computer systems with various architectures. However, there has been little effort to investigate its characteristics with respect to hardware components. This paper presents the performance scalability of SPEC CPU2000 benchmark over CPU clock speed. For an Intel x86-based system running at various clock speed, we measure the performance of SPEC CPU2000 benchmark, and analyze the characteristic of SPEC CPU2000 in a system aspect. In the experiment, we found that the overall performance of SPEC CPU2000 increases monotonically and linearly as the CPU clock speed increases and that the scale efficiencies of SPEC CPU2000 component benchmarks are quite evenly distributed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.74-80
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• 2002

VLSI intergrated circuits like SOC(system on chip) often require a multi-clock design style for functional or performance reasons. The problems of the clock domain transition due to clock skew and clock ordering within a test cycle may result in wrong results. This paper describes a new BIST(Built-in Self Test) architecture for multi-clock systems. In the new scheme, a clock skew is eliminated by a multi-capture. Therfore, it is possible to perform at-speed test for both clock inter-domain and clock intra-domain.

• Journal of Internet Computing and Services
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• v.5 no.4
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• pp.35-42
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• 2004

In this paper the more accurate models than any other ones so far have been proposed for the performance evaluation of single-buffered banyan-type Multistage Interconnection Networks(MINs)'s under nonuniform traffic condition is obtained. Small clock cycle instead of big clock cycle is used. The accuracy of proposed models are conformed by comparing with the results from simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.245-249
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• 2004

In this paper, we have proposed a clock recovery algorithm of Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio(OFDM/QPSK-DMR) system using Band Limited-Pulse Shaping Filter(BL-PSF) and compared the clock phase error variance of OFDM/QPSK-DMR system with that of single carrier DMR system. The OFDM/QPSK-DMR system using windowing method requires training sequence or Cyclic Prefix (CP) to synchronize the clock phase of received signal. But transmit efficient is increased in our proposed DMR system because of no using redundant data such as training sequence or CP. The proposed clock recovery algorithm is simply realized in the OFDM/QPSK-DMR system using BL-PSF. The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DR system under Additive White Gaussian Noise(AWGN) environment.

• ETRI Journal
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• v.30 no.3
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• pp.461-468
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• 2008

This paper presents a chromatic dispersion monitoring technique using a clock-frequency component for carrier-suppressed return-to-zero (CSRZ) signal. The clock-frequency component is extracted by a clock-extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high-speed optical communication systems.