• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.26-30
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• 2006

For the purpose of developing capacitive humidity sensor having interdigital electrodes, interdigital electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thickness. For the development of ASIC, switched capacitor signal processing circuits for capacitive humidity sensor were designed and simulated by Cadence using $0.25{\mu}m$ CMOS process parameters. The signal processing circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control. The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is $0.4%R.H./^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of $3%R.H.{\sim}98%R.H.$. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigital electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc.

• International Journal of Precision Engineering and Manufacturing
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• v.8 no.4
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• pp.22-26
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• 2007

We describe a new way of implementing absolute displacement measurements by exploiting the optical comb of a femtosecond pulse laser as a wavelength ruler, The optical comb is stabilized by locking both the repetition rate and the carrier offset frequency to an Rb clock of frequency standard. Multiwavelength interferometry is then performed using the quasi-monochromatic beams of well-defined generated wavelengths by tuning an external cavity laser diode consecutively to preselected light modes of the optical comb. This scheme of wavelength synthesizing allows the measurement of absolute distances with a high precision that is traceable to the definition of time. The achievable wavelength uncertainty is $1.9{\times}10^{-10}$, which allows the absolute heights of gauge blocks to be determined with an overall calibration uncertainty of 15 nm (k = 1). These results demonstrate a successful industrial application of an optical frequency synthesis employing a femtosecond laser, a technique that offers many possibilities for performing precision length metrology that is traceable to the well-defined international definition of time.

• Journal of Astronomy and Space Sciences
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• v.34 no.1
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• pp.19-30
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• 2017

The optical wide-field patrol network (OWL-Net) is a Korean optical surveillance system that tracks and monitors domestic satellites. In this study, a batch least squares algorithm was developed for optical measurements and verified by Monte Carlo simulation and covariance analysis. Potential error sources of OWL-Net, such as noise, bias, and clock errors, were analyzed. There is a linear relation between the estimation accuracy and the noise level, and the accuracy significantly depends on the declination bias. In addition, the time-tagging error significantly degrades the observation accuracy, while the time-synchronization offset corresponds to the orbital motion. The Cartesian state vector and measurement bias were determined using the OWL-Net tracking data of the KOMPSAT-1 and Cryosat-2 satellites. The comparison with known orbital information based on two-line elements (TLE) and the consolidated prediction format (CPF) shows that the orbit determination accuracy is similar to that of TLE. Furthermore, the precision and accuracy of OWL-Net observation data were determined to be tens of arcsec and sub-degree level, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.675-681
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• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.88-97
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• 2000

We have proposed and analysed a novel Lookup Algorithm which had a short switching speed and tiny memory size for IP router. This algorithm could simply be implemeted by a hardware with SRAM because of simple structure. This Lookup scheme needs 1${\sim}$3 memory access times. When we simulated with 40,000 routing record obtained from IPMA Website, the maximum memory size of this algorithm was 316KB(the offset threshold for compression algorithm was 8). When we simulated by HDL using ALTERA EPM7256 series and 100MHz clock and SRAM of 10ns access time, the total lookup time was 45ns for two memory access, 175ns for three memory access.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.144-148
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• 2001

For the purpose of developing capacitive humidity sensor having interdigit electrodes, interdigit electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thichness. For the development of ASIC, switched capacitor signal conditioning circuits for capacitive humidity sensor were designed and simulated by cadence using 0.25um CMOS process parameters. The signal conditioning circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is 0.4%R.H./$^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of 3%R.H. ${\sim}$ 98%R.H.. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigit electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc..

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.96-101
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• 2003

This paper is on the user equipment (UE) side time tracker design and implementation of the wideband code division multiple access (WCDMA) system. The time tracker is constructed as a second order closed loop including time error detector (TED), loop filter (LP), numerically controlled oscillator (NCO), and sample selector (SS). Through the simulation, we found the gain of the TED as a function of the CPICH power contribution to the total transmission power of the base station. Also we derived the transfer function of the loop and the BER versus DPCH power relationships where timing offsets and loop noise bandwidths are used as parameters. In the curve, we can conclude that there are appropriate loop noise bandwidths according to the given environments for the better performance.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.3
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.