• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.73-76
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• 2000

In tendency of digitalization, we studied about the purpose of digital modem for MRI spectrometer and advantage of digital modem compared with analog one. We introduce requirements lot designing transmitter of high speed digital modem for MRl spectrometer We also introduce its top-level and mid-level architecture. The transmitter is composed of CPC-P interface block, DUC & DAC block, RF block, master clock generation block, MCU block. Especially, DUC and its control parts are studied in detail. DUC and DAC can operate up to 52MHz and 100Msps, respectively. However we uses 35MHz as master clock and this paper shows its validity through simulations.

• Journal of Astronomy and Space Sciences
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• v.30 no.2
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• pp.113-121
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• 2013

Heumgyeonggaknu is a water-hammering type automatic water clock which was made by Jang Yeong-Sil in 1438. The water clock that is located in Heumgyeonggaknu consists of Suho which is equipped with 2-stage overflow. Constant water wheel power is generated by supplying a fixed amount of water of Suho to Sususang, and this power is transferred to each floor at the same time. The 1st floor rotation wheel of Gasan consists of the operation structure which has the shape of umbrella ribs. The 2nd floor rotation wheel is made so that the 12 hour signal, Gyeong-Jeom signal, and Jujeon constitute a systematic configuration. The 3rd floor rotation wheel is made so that the signal and rotation of Ongnyeo and four gods can be accomplished. Based on the above conceptual design, this paper analyzed the internal signal generation and power transmission of Heumgyeonggaknu.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2005.11a
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• pp.249-254
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• 2005

본 논문은 디지털 방송 프로그램 진행 중 비디오의 특정 시점에 동기화된 특정 객체의 위치정보를 표현하는 data stream을 생성하고, 그 시점에 해당 위치 정보를 해석하는 해석기에 관한 것이다. 현재의 상용 스트림 생성기는 디지털 방송 표준에서 권고하는 스트림 이벤트의 발생 시각과 셋톱박스에서 디코딩 시에 사용할 참조값을 적절하게 생성하지 못하고 있다. 또한, 셋톱박스에서 동작하는 애플리케이션(Xlet) 역시 STC(System Time Clock), PCR(Program Clock Reference), NPT(Normal Play Time) 등의 시간값을 적절하게 읽어내지 못하고 있다. 더욱이, 현재의 디지털 방송 표준에서는 영상 내 특정 객체를 위해 정보를 제공하는 데에는 한계가 있다. 따라서, 본 논문에서는 다양한 연동형 디지털 방송 프로그램 제작을 위해 비디오의 특정 시점에 동기화된 객체의 위치정보를 표현하는 data stream을 생성하는 방법과, 동기화된 데이터를 처리하는 애플리케이션에 대해서 설명한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1102-1106
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• 2004

Main component of phase time error of clocks in communication systems is flicker noise. This paper describes computer simulation algorithm of clock error. First, the standard for clock stability is introduced. Flicker noise is generated from white noise sequences by means of an algorithm. Relation between stage number, time constant and bandwidth are introduced. With the help of this algorithm, flicker noise is generated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.1
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• pp.245-251
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• 2015

In this paper, we present a design of PWM-controlled driving device for backlights in LED systems. The system can control either the brightness of the entire screen of backlights of LCD driven by LED or illumination or contrast of each partial segment of the entire screen. The PWM-controlled driving device includes the shift register that shifts the series data according to the clock signal prior to the generation of parallel data. It is also is comprised of a number of registers, a number of counters, a number of comparators, and a number of synchronizing gates (producing the PWM-controlled signals). The proposed device for backlights in LED systems can generate the PWM-controlled signal with a high degree of resolution without the increase of clock frequency. It also contains the PWM-controlled circuit that disperses and restrains the quantized noise.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.133-140
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• 2020

We discuss the method of a high precision range trigger and generation for a high range resolution radar. To verify the designed range resolution performance, we use test-equipments which can absolutely make a precision range shorter than the desined range resolution. The accuracy of generated range is proportional to the system reference clock. However, the system main processor is limited to input reference clocks and a higher available one is expensive in the conventional method. To solve this problem, we proposed that the range trigger and generation method using multi-phase-shiftings and integration. Through a experiment, we verified that the proposed method made problems which can be ocurred in the conventional method clear.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.1
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• pp.139-146
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• 2003

In this paper we demonstrate a cryptanalysis of the stream cipher LILI-128. Our approach to analysis on LILI-128 is to solve an overdefined system of multivariate equations. The LILI-128 keystream generato $r^{[8]}$ is a LFSR-based synchronous stream cipher with 128 bit key. This cipher consists of two parts, “CLOCK CONTROL”, pan and “DATA GENERATION”, part. We focus on the “DATA GENERATION”part. This part uses the function $f_d$. that satisfies the third order of correlation immunity, high nonlinearity and balancedness. But, this function does not have highly nonlinear order(i.e. high degree in its algebraic normal form). We use this property of the function $f_d$. We reduced the problem of recovering the secret key of LILI-128 to the problem of solving a largely overdefined system of multivariate equations of degree K=6. In our best version of the XL-based cryptanalysis we have the parameter D=7. Our fastest cryptanalysis of LILI-128 requires $2^{110.7}$ CPU clocks. This complexity can be achieved using only $2^{26.3}$ keystream bits.