• 제목/요약/키워드: Clock bias

검색결과 55건 처리시간 0.017초

Elimination of Clock Jump Effects in Low-Quality Differential GPS Measurements

  • Kim, Hee-Sung;Lee, Hyung-Keun
    • Journal of Electrical Engineering and Technology
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    • 제7권4호
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    • pp.626-635
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    • 2012
  • Most of single frequency GPS receivers utilize low-quality crystal oscillators. If a lowquality crystal oscillator is utilized as the time reference of a GPS receiver, the receiver's clock bias grows very fast due to its inherent low precision and poor stability. To prevent the clock bias becoming too large, large clock jumps are intentionally injected to the clock bias and the time offset for clock steering purpose. The abrupt changes in the clock bias and the time offset, if not properly considered, induce serious accuracy degradation in relative differential positioning. To prevent the accuracy degradation, this paper proposes an efficient and systematic method to eliminate the undesirable clock jump effects. Experiment results based on real measurements verify the effectiveness of the propose method.

Assisted GNSS Positioning for Urban Navigation Based on Receiver Clock Bias Estimation and Prediction Using Improved ARMA Model

  • Xia, Linyuan;Mok, Esmond
    • 한국항해항만학회:학술대회논문집
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    • 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.1
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    • pp.395-400
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    • 2006
  • Among the various error sources in positioning and navigation, the paper focuses on the modeling and prediction of receiver clock bias and then tries to achieve positioning based on simulated and predicted clock bias. With the SA off, it is possible to model receiver clock bias more accurately. We selected several types of GNSS receivers for test using ARMA model. To facilitate prediction with short and limited sample pseudorange observations, AR and ARMA are compared, and the improved AR model is presented to model and predict receiver clock bias based on previous solutions. Our work extends to clock bias prediction and positioning based on predicted clock bias using only 3 satellites that is usually the case under urban canyon situation. In contrast to previous experiences, we find that a receiver clock bias can be well modeled using adopted ARMA model. Test has been done on various types of GNSS receivers to show the validation of developed model. To further develop this work, we compare solution conditions in terms of DOP values when point positioning is conducted using 3 satellites to simulate urban positioning environment. When condition allows, height component is derived from other ways and can be set as known values. Given this condition, location is possible using less than 2 GNSS satellites with fixed height. Solution condition is also discussed for this background using mode of constrained positioning. We finally suggest an effective predictive time span based on our test exploration under varied conditions.

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시계 바이어스 변화율을 이용한 반송파 DGPS의 성능 향상 (Performance Improvement of Carrier phase DGPS Using Clock Bias Drift)

  • 신용설;박찬국
    • 한국항공우주학회지
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    • 제33권12호
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    • pp.61-67
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    • 2005
  • 본 논문에서는 GPS 신호가 자주 단절되는 환경하에서도 안정한 위치 해를 제공하는 반송파 DGPS 방법을 제안한다. 시계 바이어스 변화율을 이용하여 큰 오차가 포함된 측정치 채널을 제거함으로써 더욱 정확한 위치 해를 제공하는 알고리듬을 구현하였다. 가시위성의 앙각과 시계 바이어스 변화율의 관계를 살펴보고, 적절한 임계치를 제안하였으며, 구현된 알고리듬이 실데이터에서도 성능이 우수함을 상용프로그램과 비교하여 보였다.

A GHz-Level RSFQ Clock Distribution Technique with Bias Current Control in JTLs

  • Cho W.;Lim J.H.;Moon G.
    • 한국초전도ㆍ저온공학회논문지
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    • 제8권2호
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    • pp.17-19
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    • 2006
  • A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

An Approach for GPS Clock Jump Detection Using Carrier Phase Measurements in Real-Time

  • Heo, Youn-Jeong;Cho, Jeong-Ho;Heo, Moon-Beom
    • Journal of Electrical Engineering and Technology
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    • 제7권3호
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    • pp.429-435
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    • 2012
  • In this study, a real-time architecture for the detection of clock jumps in the GPS clock behavior is proposed. GPS satellite atomic clocks have characteristics of a second order polynomial in the long term showing sudden jumps occasionally. As satellite clock anomalies influence on GPS measurements which could deliver wrong position information to users as a result, it is required to develop a real time technique for the detection of the clock anomalies especially on the real-time GPS applications such as aviation. The proposed strategy is based on Teager Energy operator, which can be immediately detect any changes in the satellite clock bias estimated from GPS carrier phase measurements. The verification results under numerous cases in the presence of clock jumps are demonstrated.

IF 조합 측정치를 사용하는 단독 정밀 측위 오차해석 (An Error Analysis of Precise Point Positioning using Ionosphere Free Combination Measurements)

  • 박슬기;조득재;신영철;박찬식
    • 제어로봇시스템학회논문지
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    • 제18권9호
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    • pp.871-877
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    • 2012
  • An error analysis of PPP (Precise Point Positioning) using IF (Ionosphere Free) combination is given in this paper. It is shown that the performance of the ordinary model with positions, clock bias, integer ambiguities and ionosphere delay as unknowns is equivalent to that of an ionosphere difference combination where ionosphere delay is cancelled out. Furthermore, it is shown that IF combination is an ionosphere difference combination but not unique. It is also proved that all difference models show same performances. The error analysis evaluated with a hardware simulator and real measurements show that the ionosphere delay is effectively eliminated by IF combination or equivalently by the ionosphere difference combination. However, if bias errors such as troposphere, clock bias or multipath are included in the measurements, the performance of the IF combination is degraded because the bias errors are amplified by the ionosphere difference operation.

A Short-Term Prediction Method of the IGS RTS Clock Correction by using LSTM Network

  • Kim, Mingyu;Kim, Jeongrae
    • Journal of Positioning, Navigation, and Timing
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    • 제8권4호
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    • pp.209-214
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    • 2019
  • Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

저전력 무선통신 모뎀 구현용 전류기억소자 성능개선 (Performance Improvement of Current Memory for Low Power Wireless Communication MODEM)

  • 김성권
    • 한국전자통신학회논문지
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    • 제3권2호
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    • pp.79-85
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    • 2008
  • 다양한 무선통신 방식이 출현함에 따라 배터리 수명과, 저전력 동작이 중요시되면서 무선 통신용 LSI는 SI circuit을 이용하는 analog current-mode signal processing을 주목하고 있다. 그러나 SI (Switched-Current) circuit을 구성하는 current memory는 clock-feedthrough의 문제점을 갖는다. 본 논문에서는 current memory의 문제점인 clock-feedthrough의 일반적인 해결방안으로 CMOS switch의 연결을 검토하고, current memory 성능 개선의 설계방안을 제안하기 위하여 CMOS switch 간의 width의 관계를 도출하고자 한다. Simulation 결과, memory MOS의 width가 20um, input current와 bias current의 ratio가 0.3, CMOS switch nMOS의 width가 2~6um일 경우에 CMOS switch 간의 width는 $W_{Mp}=5.62W_{Mn}+1.6$의 관계로 정의되고, CMOS switch nMOS의 width가 6~10um일 경우에 CMOS switch 간의 width는 $W_{Mp}=2.05W_{Mn}+23$의 관계로 정의되는 것을 확인하였다. 이 때 정의된 MOS transistor의 관계는 memory MOS의 성능향상을 위한 설계에 유용한 지침이 될 것으로 기대된다.

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Dilution of Precision Relationship between Time Difference of Arrival and Time of Arrival Techniques with No Receiver Clock Bias

  • Choi, Heon Ho;Jin, Mi Hyun;Lim, Deok Won;Lee, Sang Jeong;Park, Chansik
    • Journal of Electrical Engineering and Technology
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    • 제11권3호
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    • pp.746-750
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    • 2016
  • Dilution of Precision (DOP), as a measure of positioning accuracy, is an essential factor. Therefore, the DOP relationship between systems is very important. In this paper, the DOP relationship between TDOA and TOA in systems lacking clock bias is derived analytically and verified experimentally. Also, using those of earlier studies, the DOP relationship in each of defined systems is derived analytically.