• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• 한국HCI학회:학술대회논문집
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• 2006.02a
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• pp.1373-1378
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• 2006

대용량의 네트워크 인프라가 확대되고, 네트워크를 통한 DV, HD 급의 고화질 비디오 전송이 보편화 되면서, 고화질의 비디오에 몰입감, 현실감을 증진시키기 위한 스테레오 HD 비디오 전송이 가능하게 되었다. 본 논문은 IP 네트워크를 통해서 스테레오 HD 비디오 전송을 가능하게 해주는 소프트웨어 기반의 HD 비디오 전송 시스템에서 효과적으로 몰입감과 입체감을 제공하기 위해 충족되어야 하는 좌우 영상의 동기화에 필요한 요소들을 다룬다. 제안된 동기화 기법은 수신 측에서 최종적으로 동기화된 좌우 영상을 통해 스테레오 HD 비디오를 얻기 위해서 좌우 카메라로부터 영상의 획득 시, 획득된 영상의 네트워크 전송 시, 또 수신된 영상의 재생 시 좌우 영상의 동기화한다. 결과적으로 동기화 된 좌우 영상을 통하여 몰입감과 현실감을 가지는 스트레오 HD 비디오를 실시간으로 감상할 수 있다.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.11
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• pp.963-968
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• 2003

A feedback control implementation for a high speed train pressurization system is proposed based on CAN (Controller Area Network). Firstly, system model including network latencies by CAN arbitration mechanisms is proposed, and an analytical compensation method of control parameters based on the system model is proposed for the network latencies. For the practical implementation of the control, global synchronization is adopted for controller to measure network latencies and to utilize them for the compensation of the control parameters. Simulation results are shown with practical tunnel data response. The proposed method is evaluated to be the most effective for the system through the control performances comparing among a controller not considering network latencies, other two off-line compensation methods, and the proposed method.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.07a
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• pp.69-72
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• 2013

본 논문은 TPSN 알고리즘의 시각 동기화 오차를 개선하기 위하여 Imote2 센서 노드의 클럭 드리프트 특성을 적용하는 개선된 TPSN 알고리즘을 제안한다. 클럭 드리프트의 원인은 주로 수정발진기에 기인한다. 본 연구에서는 온도 및 습도 등 환경 조건이 비슷할 경우에 드리프트가 크게 차이나지 않는다는 실험 결과에 따라 드리프트의 평균값을 구하고 이를 TPSN 동기화 오차 보정에 사용한다. 이때 적용되는 드리프트 특성 값은 센서 노드 설치 이전에 미리 측정하여야 한다. 실험을 통하여 본 논문에서 제안한 개선된 TPSN 알고리즘이 동기화 오차 개선에 효과적임을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.26-33
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• 1992

This paper describes a new phase-difference detection method and the associate process algorithm for calculating the mean value of phase difference detected and OVCXO control value and for monitoring and controlling the DP-PLL operation status to be used in the design of a high-frequency DP-PLL. Through the experiments of DP-PLL implemented with 16-bit processor, memories, pheriperals and OVCXO to eraluate the suggested method and algorithm, it is shown that a remarkable improvement in PLL function such as phase detection, and reference clock tracing capability, jitter absorbability and frequency stability compared with other existing DP-PLL synchronization device is achieved.

• ETRI Journal
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• v.31 no.4
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• pp.466-468
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• 2009

In this letter, we propose a one-way ranging algorithm that is based on wireless synchronization with measured timestamps and clock frequency offsets. In our proposed algorithm, an active mobile node initiates a ranging procedure by transmitting a ranging frame, and the anchor nodes report their timestamps for the received ranging frame to a reference anchor node. The synchronization of a pair of nodes is provided with instantaneous time information, and the corresponding difference of distances can be calculated.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1877-1883
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• 1999

Synchronization of the clock at the ATM receiving terminal is studied. The technique analyzed here has been adapted by ITU-T as the standard for ATM timing recovery. This paper presents analysis of SRTS method itself and jitter in SRTS. The power pectrum and rms amplitude of SRTS jitter are calculated. The calculated average rms value for T1 1.544MHz source signal is 32.63ns and 0.15ns for E4 139.264MHz signal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.8
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• pp.1503-1510
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• 2007

To implement a high-precision lightning tracking system utilizing TDOA measurements, high-speed data acquisition and precise timing synchronization between ground sensors should be achieved. At the same time, considering the size of digitizer's memory, the data memory needs to be managed so that only the sampled data around the occurrence of stepped leader pulse is stored. This paper presents a detection-and-acquisition system for lightning signals that is the main equipment of ground sensor in lightning tracking system. GPS clock module is used to get precise timing synchronization and the 500MHz high speed digitizer is employed. In order to detect the leading edge of the lightning pulse and save the sampled data and its timing, lightning detection module is implemented and multi-record method is employed in the proposed system. Field experiment results show that the proposed system can detect and save the lightning signal efficiently.