• The KIPS Transactions:PartC
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• v.18C no.2
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• pp.119-126
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• 2011

In wireless sensor networks Time synchronization used to be performed after routing tree is constructed. It results in increasing the number of packets and energy consumption. In this paper, we propose a time synchronization algorithm combined with flooding routing tree construction algorithm, which applies LTS (Lightweight Time Synchronization) information packed into the forwarding and backward routing packets. Furthermore, the proposed algorithm compensates the time error due to clock drift using the round time with fixed period. We prove that the proposed algorithm could synchronize the time of among sensor nodes more accurately compared to TSRA (Time Synchronization Routing Algorithm) using NS2 simulation tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.63-68
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• 2004

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.1-10
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• 2007

This paper describes the development of a network-based passenger information system(PIS) which provides the convenience of the passenger of the train and heightens the effect of the subtitle service, the advertising and the shelter guidance broadcasting against the urgent event. The existing system uses VGA signal distributor in order to broadcast information with image and subtitle and voice guidance. In this paper we improve the existing system by applying the UDP and TCP/IP protocol and use a reference clock to solve a data loss and synchronization problem which occurs in this case. We also developed an XML-based subtitle authoring tool which can edit and play the subtitles with various 3D to improve the automatic guidance broadcasting and advertisement effect according to the operation schedule of the train. The system performance was evaluated through a simulation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.220-222
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• 2003

최근 무선 임베디드 시스템의 사용이 증가하면서 기존의 분산 환경에 무선 임베디드 시스템이 포함되기 시작하였고, 이를 고려한 분산 어플리케이션들이 개발되고 있다. Global clock과 동기화할 수 있는 GPS가 모든 무선 임베디드 시스템에 장착되지 않은 상황에서 분산된 임베디드 시스템간 혹은 고성능 컴퓨터와의 내부 동기화를 수행할 동기화 기법이 필요하다. 현재 무선환경에서의 동기화에 대한 연구들이 이루어지고 있지만 제한된 리소스의 임베디드 시스템에 그대로 적용하기 어렵다. 이에 본 논문에서는 무선 임베디드 시스템만이 가지는 제한사항을 고려하여 메시지 지연값의 변화량을 측정하여 적용할 수 있는 시간 동기화 기법을 제시하고 실험을 통해 그 성능을 평가한다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.1-9
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• 1993

For frame synchronization in synchronous multiplexer based on SDH (Synchronous Digital Hierarchy), pointer justification mechanism (opinter adjustment) to compensate small frequency differences between the received uline clock and local clock is sed. But these pointer adjustment will introduce jitter onto tributary signal. This paper presents the bit leaking method to reduce those jitter to a level compatible with existing specification, where the simulation shows that this method reduces pointer adjustment jitter.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.11a
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• pp.335-342
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• 2000

멀티미디어 정보를 처리하기 위해서 필수적으로 필요한 기술이 멀티미디어 동기화를 구성하는 것이다. 본 논문에서는 두 시스템 사이의 클럭 동기를 맞추어 주기 위하여 가상 클럭(VGC : Virtual Global Clock)을 제안하였다. Loop flack 방법에 의한 제안된 가상 클럭은 통신이 가능한 모든 환경에 적용할 수 있다

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.859-866
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• 1988

A high speed frame synchronization system has been realized which generates the frame sync clock from 565Mb/s data stream (the DS-5 digital multiplex hierarchy signal). The design of a frame pattern detector using a parallel detection method brings into low speed operation and resolves the problems due to the high speed operation. The frame synchronization algorithm recommended by CCITT is also realized by designing a sync mode controller. Appropriate design procedures are considered for an efficient hardware design and minimized connection lines. The CAD simulation as well as experiment show that the performance of the newly designed frame synchronization system satisfies the relevant requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.475-484
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• 1990

This paper proposes a method for the implementation of a power line communication equipment using power line synchronization in a direct-sequence spread spectrum communication system. In order to implement a network using a power line as a transmission channel we have investigated the utilization of direct-sequence speread spctrum which gives such advantages as robustness against narrow-band interference and noise, and realization of multiple access. In a power line, however, complexity of synchronization makes it difficult to realize a multiple access and cost down and system simplification. The proposed technique of power line synchronization makes it possible to get cost down and system size small, and the realization of multiple communication can be achieved by the addition of address setting circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.4
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• pp.644-650
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• 2001

A remotely located synchronization system which is locked to the remote master clock has been implemented by using GPS Common-View technique. The measurement results showed that the accuracy of the remote synchronization system could be kept within a few parts in $10^{-12}$ and MTIE(Maximum Time Interval Error) met the ITU-T Recommendation(G.811). A prototype system having fully automatic operational functions has been realized up to now and is expected to be used in the network synchronization in the near future.