• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.17 no.1
• /
• pp.38-46
• /
• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.

• Journal of Institute of Control, Robotics and Systems
• /
• v.15 no.11
• /
• pp.1144-1149
• /
• 2009

This paper deals with the time synchronization problem over SpaceWire links. SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper, faster on-board data handling in spacecraft. The standard defines Time-Code for time distribution over SpaceWire network. When a Time-Code is transmitted, transmission delay and jitter is unavoidable. In this paper, a mechanism to remove Time-Code transmission delay and jitter over SpaceWire links is proposed and implemented with FPGA for validation. The proposed mechanism achieves high resolution clock synchronization over SpaceWire links, complies with the standard and can be easily adopted over SpaceWire network.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.12B
• /
• pp.1037-1041
• /
• 2004

In this paper we propose a new conceptual slave clock system in which remotely located clock is synchronized to the reference clock by intermediation of the satellite time, show a probability of adoption to real network by experiments. This new proposed method has lots of structural advantages over the existing methods because all of the node clocks can be maintained with the same hierarchical quality. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts in 1012 and that the MTIE (Maximum Time Interval Error) meets the ITU-T Recommendation G.811 for the primary reference clock A prototype system having fully automatic operational functions has been realized, and it is expected to be commercially used as a node clock for synchronization in the digital communication network in the near future.

• Journal of the Korea Society of Computer and Information
• /
• v.13 no.1
• /
• pp.175-183
• /
• 2008

QoS-support technology in networks is based on measuring QoS metrics which reflect a magnitude of stability and performance. The one-way delay measurement of the QoS metrics especially requires a guarantee of clock synchronization between end-to-end hosts. However, the hosts in networks have a relative or absolute difference in clock time by reason of clock offsets. flock skews and clock adjustments. In this paper, we present a theorem, methods and simulation results of one-way delay and clock offset estimations between end-to-end hosts. The proposed theorem is a relationship between one-way delay, one-way delay variation and round-trip time And we show that the estimation error is mathematically smaller than a quarter of round-trip time.

• The KIPS Transactions:PartC
• /
• v.13C no.3 s.106
• /
• pp.303-310
• /
• 2006

This paper is to execute a study for characteristic analysis of synchronization clock and maximum network node number with various clock states, normal, SPT, LPT, in NG-SDH networks. Through the simulations, maximum network node numbers showed from 42 to 38 nodes in normal state. In SPT state, maximum network node numbers, when the last NE network applied to only SPT state, presented from 19 to 4 nodes, much less than normal state. Node numbers to meet specification in case of occurrence of SPT state in all NE networks decreased greatly. In LPT state, all maximum node numbers, when the last NE network applied to only LPT state, presented more than 50 nodes, and the results in case of occurrence of LPT state in all NE networks were also identified. However, node numbers to meet specification in case of LPT state in all DOTS networks were few large with difference between LPT and normal or SPT state.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.5
• /
• pp.787-795
• /
• 1994

In this paper, we have proposed a bit synchronization algorithm which extracts the synchronized clock for random NRZ signal and designed a circuit followed by its performance analysis. The synchronization circuit consists of the Data Transition Detector and Mod 64 Counter, Phase Comparison and Controller, 64 Divider. The data input rate and master clock rate are 16 Kbps and 4.096MHz, respectively. The phase is compensated by 1/64 of the data signal period for every data bit. Through a series of experiments, the maximum immunity of phase jiter for input signal and the deviation of the recovered clock are measured 23.8% and 1.6%, respectively. The fully digital synchronization circuit is simple to implement into signal IC chip and also effective for the low speed digital mobile communications.

• The Journal of the Korea Contents Association
• /
• v.5 no.4
• /
• pp.227-236
• /
• 2005

We study, in terms of VoIP user assessment of voice quality, the synchronization of measurement system is important. Commonly the synchronization system uses NTP(Network Time Protocol) or GPS(Global Positioning System), these synchronization method has time error of distance, system overhead of data processing, and system specialized clock error. we propose and implement the synchronization method to correct time error between two measurement system in the internet. So the time synchronization of systems can get time error, then user assessment of voice quality become reliable.

• Journal of Communications and Networks
• /
• v.7 no.1
• /
• pp.1-12
• /
• 2005

Ethernet is being deployed in metropolitan area networks (MANs) as a lower-cost alternative to SONET-based infrastructures. MANs are usually required to support common communication services, such as voice and frame relay, based on legacy synchronous TDM technology in addition to asynchronous packet data transport. This paper addresses the clock synchronization problem that arises when transporting synchronous services over an asynchronous packet infrastructure, such as Ethernet. A novel algorithm for clock synchronization is presented combining time-stamp methods used in the network time protocol (NTP) with signal processing techniques applied to measured packet interarrival times. The algorithm achieves the frequency accuracy, stability, low drift, holdover performance, and rapid convergence required for viable emulation of TDM circuit services over Ethernet.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.38 no.7
• /
• pp.785-797
• /
• 2014

Support for the precise time synchronization of EtherCAT, known as distributed clock (DC), enables the design of highly synchronized operations in distributed real-time systems. This study evaluates the performance of the EtherCAT DC through extensive experiments in a real automation system. We constructed an EtherCAT control system using Xenomai and IgH EtherCAT stack, and analyzed the clock deviation for different devices in the network. The results of the evaluation revealed that the accuracy of the synchronized clock is affected by several factors such as the number of slave devices, period of drift compensation, and type of system time base. In particular, we found that careful decision regarding the system time base is required because it has a fundamental effect on the master operation, which results in significantly different performance characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.5A
• /
• pp.561-570
• /
• 2008

Time synchronization is essential for a number of network applications such as high speed communication and parallel/distribution processing systems. As the era of ubiquitous computing is ushered in, the high precise time synchronization in wireless networks have been required in. This paper presents the design ana the implementation of the high precision time synchronization in wireless networks using ZigBee. To achieve high precision requirements, we have tried to analyze and reduce error factors such as the latency and jitters of a protocol stack on wireless environments. In addition, this paper includes some experiments and performance evaluations of our system. The result is that we established for nodes in a network to maintain their elects to within a 50 nanosecond offset from the reference clock.