• Title/Summary/Keyword: Clock Synchronization

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A Radiation-hardened Model Design of CMOS Digital Logic Circuit for Nuclear Power Plant IC and its Total Radiation Damage Analysis (원전용 IC를 위한 CMOS 디지털 논리회로의 내방사선 모델 설계 및 누적방사선 손상 분석)

  • Lee, Min-Woong;Lee, Nam-Ho;Kim, Jong-Yeol;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.67 no.6
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    • pp.745-752
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    • 2018
  • ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

Asynchronous Ranging Method using Estimated Frequency Differences in Wireless Sensor Networks (무선 센서망에서의 주파수 차이 추정 비동기 Ranging 방식)

  • Nam, Yoon-Seok;Huh, Jae-Doo
    • The KIPS Transactions:PartC
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    • v.15C no.1
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    • pp.31-36
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    • 2008
  • The clock frequency difference of sensor nodes is one of main parameters in TOF estimation and affect to degrade ranging algorithms to estimate positions of mobile nodes in wireless sensor networks. The specification of IEEE802.15.4a describes asynchronous TWR and SDS-TWR insensitive to frequency difference without any additional network synchronization. But the TWR and SDS-TWR can not eliminate sufficiently the effect of frequency difference of node pair, packet processing delay and its difference. Especially use of low cost oscillator with wide range offset, sensor node with different hardware and software can make the positioning errors worse. We propose an estimation method of frequency differences, and apply the measured frequency differences to TWR and SDS-TWR. We evaluate the performance of the proposed algorithm with simulation, and make certain that the proposed method enhances the performance of existing algorithms with positioning errors less than 25 cm.

Analysis of Comparisons of Estimations and Measurements of Loran Signal's Propagation Delay due to Irregular Terrain (Loran 신호의 지형에 의한 전파 지연 예측 및 실측 비교 분석)

  • Yu, Dong-Hui
    • Journal of the Institute of Convergence Signal Processing
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    • v.12 no.2
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    • pp.107-112
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    • 2011
  • Several developed countries have been developing their own satellite navigation systems, such as Europe's Galileo, China's BEIDOU, and Japan's QZSS, to cope with clock errors and signal vulnerabilities of GPS. In addition, modernization of Loran, eLoran, for GPS backup has been conducted. In Korea, a dependent navigation system has been required and for GPS backup, the need for utilization of time synchronization infrastructure through the modernization of Loran has been raised. Loran signal uses 100Khz groundwave. A significant factor limiting the ranging accuracy of the Loran signal is the ASF arising from the fact that the groundwave signal is likely to propagate over paths of varying conductivity and topography. Thus, an ASF compensation method is very important for Loran and eLoran navigation. This paper introduces the propagation delay model and then compares and analyzes the estimations from the propagation delay model and measured ASFs.

A Study on the Design and Implementation of Simulated Signal Generator for VHF Radar with High Interference and Immunity Characteristics (간섭신호 내성 및 격리도 특성이 우수한 초단파 레이다용 모의신호 발생장치의 설계 및 구현에 대한 연구)

  • Kim, Ki-Jung;Lee, Sung-Je;Jang, Youn-Hui
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.1
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    • pp.27-32
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    • 2019
  • This study describes the design and implementation of a simulated signal generator to demonstrate the performance of VHF band radar for the detection of small targets in RCS(Radar Cross Section). The transmission and reception antenna beam widths used in the simulated signal generating apparatus may be large, which may cause problems in the degree of isolation. Interference signal immunity and isolation characteristics are improved by considering operating conditions of VHF radar to solve isolation of antennas. Simulated signal generator performs the following: VHF radar transmission and reception correction, simulation signal generation, target Doppler, RCS and distance simulation, remote control, and GPS clock synchronization function. After the fabrication of the simulated signal generator, the main characteristics, such as the output characteristics and the reflection signal simulations, were tested. When the microwave radar assembly is completed in the future, it will be utilized for the performance evaluation of VHF radar.

Voltage-Frequency-Island Aware Energy Optimization Methodology for Network-on-Chip Design (전압-주파수-구역을 고려한 에너지 최적화 네트워크-온-칩 설계 방법론)

  • Kim, Woo-Joong;Kwon, Soon-Tae;Shin, Dong-Kun;Han, Tae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.22-30
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    • 2009
  • Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

Optimum Configuration of Single Frequency Network DMB to enhance the QoS and Service coverage (QoS 개선과 서비스 커버리지 확장을 위한 단일 주파수망 지상파 DMB 최적화 배치)

  • Cho, Young-Hun;Won, Chung-Ho;Seo, Jong-Soo
    • Journal of Broadcast Engineering
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    • v.19 no.4
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    • pp.439-452
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    • 2014
  • This paper suggests the method to extend service area by using the transmit offset delay in T-DMB single frequency network (SFN). In general, synchronization of the transmit time of all site can be done by using the reference clock of GPS, which dose not reflect the details geographical characteristics and transmit specifications of each site. Applying the site-specific transmit offset delay, we could extend the service area of SFN T-DMB. Applying the transmit offset delay, it is found that the signal quality in the region of weak receive field strength was improved and upto 4~8 km service area expansion was achieved by satisfying the minimum field strength ($45dB{\mu}V/m$) recommended by the Korea Communications Commission (KCC). Site-specific offset delay was calculated considering the geographic service area characteristics, distribution of electric field strength between neighboring sites and site-specific service target area. Experiments were carried out in order to analyze impact of calculated offset delay on the T-DMB SFN and also to confirm that the offset delay extends T-DMB service coverage. The experiment was done in metropolitan T-DMB service areas.

Conceptual Design Analysis of Satellite Communication System for KASS (KASS 위성통신시스템 개념설계 분석)

  • Sin, Cheon Sig;You, Moonhee;Hyoung, Chang-Hee;Lee, Sanguk
    • Journal of Advanced Navigation Technology
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    • v.20 no.1
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    • pp.8-14
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    • 2016
  • High-level conceptual design analysis results of satellite communication system for Korea augmentation satellite system (KASS) satellite communication system, which is a part of KASS and consisted of KASS uplink Stations and two leased GEO is presented in this paper. We present major functions such as receiving correction and integrity message from central processing system, taking forward error correction for the message, modulating and up converting signal and conceptual design analysis for concepts for design process, GEO precise orbit determination for GEO ranging that is additional function, and clock steering for synchronization of clocks between GEO and GPS satellites. In addition to these, KASS requires 2.2 MHz for SBAS Augmentation service and 18.5 MHz for Geo-ranging service as minimum bandwidths as a results of service performance analysis of GEO ranging with respect to navigation payload(transponder) RF bandwidth is presented. These analysis results will be fed into KASS communication system design by carrying out final analysis after determining two GEOs and sites of KASS uplink stations.

Gauss-Newton Based Emitter Location Method Using Successive TDOA and FDOA Measurements (연속 측정된 TDOA와 FDOA를 이용한 Gauss-Newton 기법 기반의 신호원 위치추정 방법)

  • Kim, Yong-Hee;Kim, Dong-Gyu;Han, Jin-Woo;Song, Kyu-Ha;Kim, Hyoung-Nam
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.76-84
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    • 2013
  • In the passive emitter localization using instantaneous TDOA (time difference of arrival) and FDOA (frequency difference of arrival) measurements, the estimation accuracy can be improved by collecting additional measurements. To achieve this goal, it is required to increase the number of the sensors. However, in electronic warfare environment, a large number of sensors cause the loss of military strength due to high probability of intercept. Also, the additional processes should be considered such as the data link and the clock synchronization between the sensors. Hence, in this paper, the passive localization of a stationary emitter is presented by using the successive TDOA and FDOA measurements from two moving sensors. In this case, since an independent pair of sensors is added in the data set at every instant of measurement, each pair of sensors does not share the common reference sensor. Therefore, the QCLS (quadratic correction least squares) methods cannot be applied, in which all pairs of sensor should include the common reference sensor. For this reason, a Gauss-Newton algorithm is adopted to solve the non-linear least square problem. In addition, to show the performance of the proposed method, we compare the RMSE (root mean square error) of the estimates with CRLB (Cramer-Rao lower bound) and derived the CEP (circular error probable) planes to analyze the expected estimation performance on the 2-dimensional space.

Analysis of Distributed Computational Loads in Large-scale AC/DC Power System using Real-Time EMT Simulation (대규모 AC/DC 전력 시스템 실시간 EMP 시뮬레이션의 부하 분산 연구)

  • In Kwon, Park;Yi, Zhong Hu;Yi, Zhang;Hyun Keun, Ku;Yong Han, Kwon
    • KEPCO Journal on Electric Power and Energy
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    • v.8 no.2
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    • pp.159-179
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    • 2022
  • Often a network becomes complex, and multiple entities would get in charge of managing part of the whole network. An example is a utility grid. While the entire grid would go under a single utility company's responsibility, the network is often split into multiple subsections. Subsequently, each subsection would be given as the responsibility area to the corresponding sub-organization in the utility company. The issue of how to make subsystems of adequate size and minimum number of interconnections between subsystems becomes more critical, especially in real-time simulations. Because the computation capability limit of a single computation unit, regardless of whether it is a high-speed conventional CPU core or an FPGA computational engine, it comes with a maximum limit that can be completed within a given amount of execution time. The issue becomes worsened in real time simulation, in which the computation needs to be in precise synchronization with the real-world clock. When the subject of the computation allows for a longer execution time, i.e., a larger time step size, a larger portion of the network can be put on a computation unit. This translates into a larger margin of the difference between the worst and the best. In other words, even though the worst (or the largest) computational burden is orders of magnitude larger than the best (or the smallest) computational burden, all the necessary computation can still be completed within the given amount of time. However, the requirement of real-time makes the margin much smaller. In other words, the difference between the worst and the best should be as small as possible in order to ensure the even distribution of the computational load. Besides, data exchange/communication is essential in parallel computation, affecting the overall performance. However, the exchange of data takes time. Therefore, the corresponding consideration needs to be with the computational load distribution among multiple calculation units. If it turns out in a satisfactory way, such distribution will raise the possibility of completing the necessary computation in a given amount of time, which might come down in the level of microsecond order. This paper presents an effective way to split a given electrical network, according to multiple criteria, for the purpose of distributing the entire computational load into a set of even (or close to even) sized computational loads. Based on the proposed system splitting method, heavy computation burdens of large-scale electrical networks can be distributed to multiple calculation units, such as an RTDS real time simulator, achieving either more efficient usage of the calculation units, a reduction of the necessary size of the simulation time step, or both.