• Magazine of the Korean Society of Agricultural Engineers
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• v.41 no.2
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• pp.37-43
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• 1999

This study was conducted to develop the simple and convenient irrigation control model which can maintain the appropriate rates of irrigation and drainage of nutrient solution according to the enviornmental conditions and growth stages in soilless culture of cucumber. In order to obtain fundamental data for development of the model, investigation of the actual state of soilless culture practices was carried out. Most irrigatioin systems of soillness culture were controlled by the time colock. Evapotranspiration of cucumber in soilness culture was investigated and correlations with environmental conditions were analyzed , and its estimating model was developed. In order to develop the irrigation system which can control the amount of nutrient solution applied according to seasons, weather conditions, and growth stages, a irrigation clock control was developed. Applicability of the model was tested by simulation. Drainage rates of nutrient solution controlled by conventional time clock, integrated solar radiation, and the developed model were 61% , 20%, and 32% , respectively in cucumber perlite culture.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.381-384
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• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• The Journal of the Korea Contents Association
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• v.12 no.5
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• pp.62-69
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• 2012

The newly developed field of media art is quickly making progress to include various and up-to-date forms of expression. Unlike in traditional art, the communication between the art and the viewer has become vastly important, in which the viewer is an active agent who participates and interacts with the artwork. These digital artworks can now be readily observed in everyday places and things, rather than being confined solely in the gallery space. By encouraging open interaction with the public, media art has become more accessible. Accordingly, this thesis examines the construction of a real-time multimedia clock piece using particle systems. Time has always been a significant theme in the realm of traditional art, which continues to be explored extensively in various forms of expression. In an attempt to express the continuity of time and the state of being value of existence based on technological skills, the thesis presents an artwork that uses the popular medium of a clock while also providing both usability and emotional satisfaction for the viewer's sensibility through interaction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1765-1773
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• 1997

The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.

• Journal of Positioning, Navigation, and Timing
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• v.12 no.3
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• pp.215-228
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• 2023

The State Space Representation (SSR) method provides individual corrections for each Global Navigation Satellite System (GNSS) error components. This method can lead to less bandwidth for transmission and allows selective use of each correction. Precise Point Positioning (PPP) - Real-Time Kinematic (RTK) is one of the carrier-based precise positioning techniques using SSR correction. This technique enables high-precision positioning with a fast convergence time by providing atmospheric correction as well as satellite orbit and clock correction. Currently, the positioning service that supports PPP-RTK technology is the Quazi-Zenith Satellite System Centimeter Level Augmentation System (QZSS CLAS) in Japan. A system that provides correction for each GNSS error component, such as QZSS CLAS, requires monitoring of each error component to provide reliable correction and integrity information to the user. In this study, we conducted an analysis of the performance of residual error bounding for each error component. To assess this performance, we utilized the correction and quality indicators provided by QZSS CLAS. Performance analyses included the range domain, dispersive part, non-dispersive part, and satellite orbit/clock part. The residual root mean square (RMS) of CLAS correction for the range domain approximated 0.0369 m, and the residual RMS for both dispersive and non-dispersive components is around 0.0363 m. It has also been confirmed that the residual errors are properly bounded by the integrity parameters. However, the satellite orbit and clock part have a larger residual of about 0.6508 m, and it was confirmed that this residual was not bounded by the integrity parameters. Users who rely solely on satellite orbit and clock correction, particularly maritime users, thus should exercise caution when utilizing QZSS CLAS.

• Journal of Platform Technology
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• v.12 no.2
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• pp.34-44
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• 2024

This paper proposes a dynamic clock supply control algorithm and a system load power stabilization algorithm that minimizes the power consumption of the sensing system, which accounts for the largest percentage of power consumption in mobile devices, to extend the usage time of the rechargeable battery mounted on the mobile device. The dynamic clock supply control algorithm can reduce the power consumed by the sensing system by configuring a circuit to cut off the power of the sensing system and by recognizing the state of low sensor change and adjusting the measurement cycle. The system load power stabilization algorithm is an algorithm that controls the power of the surrounding module according to the power consumption state, and when it requires a lot of power, it controls the clock supply to stabilize the operation. The experimental results confirmed that applying only the dynamic clock supply control algorithm reduces the power consumed by the sensing system by 17%, and applying only the system load power stabilization algorithm reduces power consumption by 9.3%, enabling it to operate stably in situations that require a lot of power such as image processing. When both algorithms were applied, the power consumption of the battery was reduced by 67% compared to before applying the algorithm. Through this, the reliability of the proposed method was confirmed.

• Journal of information and communication convergence engineering
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• v.11 no.3
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• pp.190-198
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• 2013

Recently, one of the most vital advancement in the field of finance is high-performance trading using field-programmable gate array (FPGA). The objective of this paper is to design high-performance Black Scholes option trading system on an FPGA. We implemented an efficient Black Scholes Call Option System IP on an FPGA. The IP may perform 180 million transactions per second after initial latency of 208 clock cycles. The implementation requires the 64-bit IEEE double-precision floatingpoint adder, multiplier, exponent, logarithm, division, and square root IPs. Our experimental results show that the design is highly efficient in terms of frequency and resource utilization, with the maximum frequency of 179 MHz on Altera Stratix V.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.6
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• pp.478-485
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• 2000

A discrete event systems (DES) is a physical system that is discrete in time and state space, asynchronous (event rather than clock-driven), and in some sense generative(or nondeterministic). This paper presents the design of fifteen modular supervisors to control an experimental CIM testbed. These supervisors are nonblocking, controllable and nonconflicting. After verification of the supervisors by simulation, the supervisors for AGV system have been implemented to demonstrate their efficacy.