• 대한치매학회지
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• 제17권3호
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• pp.100-109
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• 2018

Background and Purpose: Although the clock drawing test (CDT) is a widely used cognitive screening instrument, there have been inconsistent findings regarding its utility with various scoring systems in patients with mild cognitive impairment (MCI) or dementia. The present study aimed to identify whether patients with MCI or dementia exhibited impairment on the CDT using three different scoring systems, and to determine which scoring system is more useful for detecting MCI and mild dementia. Methods: Patients with amnestic mild cognitive impairment (aMCI), vascular mild cognitive impairment (VaMCI), mild Alzheimer's disease (AD), mild vascular dementia (VaD), and cognitively normal older adults (CN) were included. All participants were administered the CDT, the Korean-Mini Mental State Examination (K-MMSE), and the Clinical Dementia Rating scale. The CDT was scored using the 3-, 5-, and 15-point scoring systems. Results: On all three scoring systems, all patient groups demonstrated significantly lower scores than the CN. However, while there were no significant differences among patients with aMCI, VaMCI, and AD, those with VaD exhibited the lowest scores. Area under the Receiver Operating Characteristic curves revealed that the three CDT scoring systems were comparable with the K-MMSE in differentiating aMCI, VaMCI, and VaD from CN. In differentiating AD from CN, however, the CDT using the 15-point scoring system demonstrated the most comparable discriminability with K-MMSE. Conclusions: The results demonstrated that the CDT is a useful cognitive screening tool that is comparable with the Mini-Mental State Examination, and that simple CDT scoring systems are sufficient for differentiating patients with MCI and mild dementia from CN.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.193-196
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• 2001

For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.

• 전자공학회논문지C
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• 제35C권12호
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• pp.77-84
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• 1998

0.8㎛ single poly CMOS 공정을 이용하여 집적화 된 전압제어형 카오스 발생회로를 설계, 제작하였다. 제작된 카오스 집적회로는 비선형함수 발생회로와 op-amp, 2상 클럭발생회로, 2개의 샘플&홀드 회로 등으로 이루어진다. 측정결과 ±2.5V 전원, 20kHz의 클럭 인가시 입력제어전압에 따라 주기상태, 준주기 상태, 카오스 상태 등 다양한 형태의 분기현상 및 시계열 파형을 관측할 수 있었다. 또한 이 회로의 직렬, 병렬 연결에 의한 2차원 카오스 패턴도 관측하였다.

• 한국컴퓨터정보학회논문지
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• 제25권1호
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• pp.71-77
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• 2020

본 논문에서 우리는 PingPong256은 LFSR과 가변클록을 결합하여 불규칙한 PRNG를 생성하고 이를 이미지 암호화에 활용하는 방법을 제안한다. PingPong256은 2개의 LFSR을 기반으로 긴 주기가 보장되며, 가변클록은 서로 다른 LFSR의 상태를 참조하여 1회 동작시 임의의 클록만큼 동작한 결과를 출력하는 구조이다. 가변클록은 시간이 경과함에 따라 선택지가 증가하기 때문에 임의의 시간에 출력을 예측하기 어렵다는 특성으로 나타난다. PingPong256은 LFSR과 가변클록과 하드웨어 및 소프트웨어 구현의 편리함이라는 장점 및 민감성과 불규칙한 주기라는 장점을 결합한 것이다. 또한 NIST SP800-22를 사용하여 통계적 안전성을 검증하고 제안 된 방법의 안전성을 확인하고 NPCR 및 UACI를 사용하여 이미지 변화의 감도를 테스트 하였습니다.

• 제어로봇시스템학회논문지
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• 제22권8호
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• IEIE Transactions on Smart Processing and Computing
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• 제2권4호
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• 전기전자학회논문지
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• 제5권1호
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• pp.52-58
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• 2001

본 논문에서는 입력이 TTL 전압 레벨일 때 저전력으로 동작하도록 설계된 TTL-to-CMOS 입력버퍼의 회로를 제안한다. 회로 구성은 내부 활성 클럭펄스로 제어되는 반전형 입력버퍼와 래치로 구성하고, 직류 단락전류를 제거하기 위해 클럭펄스가 로우상태일 때는 입력버퍼가 동작되지 않도록 하고 하이일 때만 정상적으로 동작되도록 하였다. 시뮬레이션을 수행한 결과 제안된 회로의 전력-지연 곱이 하나의 입력당 33.7% 줄어듬을 확인하였다.

• Journal of Communications and Networks
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• 제6권2호
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• pp.93-105
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• 2004

This paper discusses cyclostationary interference suppression for multiuser wired communication systems. Crosstalk interference from digital signals in multipair cables has been shown to be cyclostationary. Many crosstalk equalization or suppression techniques have been proposed which make implicit use of the cyclostationarity of the crosstalk interferer. In this paper, the convergence and steady-state behaviors of a fractionally spaced equalizer (FSE) in the presence of multiple cyclostationary crosstalk interference are thoroughly analyzed by using the equalizer's eigenstructure. The eigenvalues with multiple cyclostationary interference depend upon the folded signal and interferer power spectra, the cross power spectrum between the signal and the interferer, and tile cross power spectrum between the interferers, which results in significantly different initial convergence and steady-state behaviors as compared to the stationary noise case. The performance of the equalizer varies depending on the relative clock phase of the symbol clocks used by the signal and multiple interferers. Measued characteristics as well as analytical model of NEXT/FEXT channel are used to compute the optimum and worst relative clock phases among the signal and multiple interferers.

• 전기학회논문지
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• 제57권8호
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• pp.1440-1446
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• 2008

In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.1002-1005
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• 2015

모바일 운영체제는 대표적으로 애플과 안드로이드 운영체제로 구분되어 왔다. 삼성은 리눅스 커널을 기반으로 하는 자체 OS 인 Tizen을 만들어서 새로운 모바일 운영체제를 선보였다. 모바일 특성상 배터리 용량의 제한 때문에 모바일 운영체제는 자체적으로 저전력을 사용하는 기술을 발전시켜 왔다. 삼성 Tizen OS는 사용자 입력이나 타임 아웃 이벤트가 발생함에 따라 LCD 상태를 조절하는 파워매니저라는 저전력 기술을 갖고 있다. 하지만 사용자 입력이 빈번할수록 LCD 상태 변경에 따른 오버헤드가 증가해 CPU 클럭이 순간적으로 증가하여 사용자 입력 전후에 에너지 소모가 급증하는 단점이 있다. 본 논문에서는 기존 Tizen OS에서 사용하는 파워매니저에 현재 LCD 상태들의 중간 상태를 추가하여, 사용자 입력이 빈번할 때 LCD 상태 변경에 따른 오버헤드를 줄이는 기법을 제안한다. 본 논문에서 제안하는 기법을 Tizen 폰 커널단에 구현하고, 사용자 LCD 터치 입력에 대해 실험하여, 사용자의 빈번한 입력에 따른 CPU클럭 증가가 감소하여 에너지를 절감할 수 있음을 보였다.