• Animal cells and systems
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• v.6 no.3
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• pp.239-245
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• 2002

Plasma melatonin, thyroid-stimulating hormone (TSH) and body temperature were measured simultaneously and continuously before and after the sleep-wake cycle was shifted in 4 healthy males and changes in the circadian rhythm itself and in the phase relationship among these circadian rhythms were determined. Normal sleep-wake cycle (sleep hours: 2300-0700) was delayed by 10 h (sleep hours: 0900-1700) during the experiment. Even after this shift the typical melatonin rhythm was maintained: low during daytime and high during night. The melatonin rhythm was gradually delayed day by day. The TSH rhythm was also maintained fundamentally during 3 consecutive days of altered sleep-wake cycle. The phase was also delayed gradually but remarkably. The daily rhythm of body temperature was changed by the alteration of sleep-wake cycle. The body temperature began to decrease at the similar clock time as in the control but the decline during night awake period was less steep and the lowered body temperature persisted during sleep. The hormonal profiles during the days of shifted sleep/wake cycle suggest that plasma melatonin and TSH rhythms are basically regulated by an endogenous biological clock. The parallel phase shift of melatonin and TSH upon the change in sleep-wake cycle suggests that a common unitary pacemaker probably regulates these two rhythms. The reversal phase relationship between body temperature and melatonin suggests that melatonin may have a hypothermic effect on body temperature. The altered body temperature rhythm suggests that the awake status during night may inhibit the circadian decrease in body temperature and that sleep sustains the lowered body temperature. It is probable but uncertain that there ave causal relationships among sleep, melatonin, TSH, and body temperature.

• Korean Journal of Optics and Photonics
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• v.13 no.4
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• pp.295-300
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• 2002

We developed an optical transmitter and receiver for an electrical time division multiplexed (ETDM) 20 Gb/s optical transmission system, and experimentally investigated their characteristics. Especially, the clock extraction circuit, which is a key component in realizing broadband optical transmission receivers, was realized by using an NRZ-to-PRZ converter implemented with a half-period delay line and an EX-OR, a high-Q bandpass filter using a cylindrical dielectric resonator, and a microstrip coupled-line bandpass filter. Finally, the bit-error-rate of demultiplexed 10 Gb/s electrical signal after back to-back transmission was measured, and a high receiver sensitivity [-26.2 dBm for NRZ ($2^{7}-1$) pseudorandom binary sequence (PRBS)] was obtained

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.279-284
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• 2003

In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• The Bulletin of The Korean Astronomical Society
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• v.41 no.1
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• pp.54.2-54.2
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• 2016

Korea Microlensing Telescope Network (KMTNet) is the first optical survey system of its kind in a way that three KMTNet observatories are longitudinally well-separated, and thus have the benefit of 24-hour continuous monitoring of the southern sky. The wide-field and round-the-clock operation capabilities of this network facility are ideal for survey and the physical characterization of small Solar System bodies. We obtain their orbits, absolute magnitudes (H), three dimensional shape models, spin periods and spin states, activity levels based on the time-series broadband photometry. Their approximate surface mineralogy is also identified using colors and band slopes. The automated observation scheduler, the data pipeline, the dedicated computing facility, related research activity and the team members are collectively called 'DEEP-South' (DEep Ecliptic Patrol of Southern sky). DEEP-South observation is being made during the off-season for exoplanet search, yet part of the telescope time is shared in the period between when the Galactic bulge rises early in the morning and sets early in the evening. We present here the observation mode, strategy, software, test runs, early results, and the future plan of DEEP-South.

• Journal of Marine Life Science
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• v.9 no.1
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• pp.47-52
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• 2024

Light is a major external environmental factor that influences the circadian rhythm of photosynthetic organisms and various physiological phenomena, such as growth, maturation, and behavior. The number of light-reaching organisms changes depending on the season and atmospheric conditions, and the intensity and wavelength of light differ depending on the organisms inhabiting the environment. Altered light changes the circadian rhythm of fish, which is controlled by clock genes, such as period 2 (Per2), cryptochrome 1 (Cry1), and melatonin. In this study, we set the zeitgeber time (ZT; 14 light-10 dark, LD) based on the actual sunrise and sunset times and examined Per2 and Cry1 activities, levels of aralkylamine N-acetyltransferase (AANAT), and melatonin in Pholis nebulosa, a drifting seaweed species exposed to irregular light. Per2 and Cry1 levels increased during the daytime and decreased after sunset. The AANAT levels decreased during the daytime and increased during the night. Melatonin concentration was highest around midnight (ZT21, 23:30), but exhibited similar concentrations during the daytime. While the activity of Per2, Cry1, and AANAT levels exhibited a typical circadian rhythm observed in most vertebrates, melatonin concentrations did not show a significant difference between the daytime and nighttime. These findings provide insights into the circadian rhythm patterns of organisms exposed to irregular light environments, such as P. nebulosa, which differ from those of typical fish species.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1643-1647
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• 2003

This paper, we propose a new high noise immunity phase-locked loop(PLL) which can suppress the high incident noise coupling with large amplitude and long period to the input frequency of PLL and keeps constant frequency and phase of the VCO output for providing the high stability distribution clock pulse.

• Journal of Information Technology Applications and Management
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• v.21 no.4
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• pp.1-13
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• 2014

This study aims to show the risk reduction effects of round-the-clock trading environment. We analyse the trading results of the currency futures contracts in CME Globex which are open 23 hours a day. These include Euro FX, Japanese Yen, Australian Dollar, and British Pound from January 2005 to August 2013. We generate new price series using only daytime prices during about 7-hour period. This hypothetical "G" data series may have greater gap risk than the original "R" data series. Empirical results show the trading risk reduction effects, that is R data series have higher profits and lower risks than G data series.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.