• 제목/요약/키워드: Clock Period

검색결과 149건 처리시간 0.03초

CMOS 회로의 전류 테스팅를 위한 내장형 전류감지기 설계 (Design of a Built-in Current Sensor for Current Testing Method in CMOS VLSI)

  • 김강철;한석붕
    • 전자공학회논문지B
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    • 제32B권11호
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    • pp.1434-1444
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    • 1995
  • Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

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저전압 DRAM용 VPP Generator 설계 (A VPP Generator Design for a Low Voltage DRAM)

  • 김태훈;이재형;하판봉;김영희
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2007년도 추계종합학술대회
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    • pp.776-780
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    • 2007
  • 본 논문에서는 저전압 DRAM용 VPP Generator의 전하펌프회로(Charge Pump Circuit)를 새롭게 제안하였다. 제안된 전하펌프회로는 2-Stage 크로스 커플 전하펌프회로(Cross-Coupled Charge Pump Circuit)이다. 4개의 비중첩 클럭신호들을 이용하여 전하전달 효율을 향상시켰고, 각 전하펌프단 마다 Oscillation 주기를 줄일 목적으로 Distributed Clock Driver인 Inverter 4개를 추가하여 펌핑전류(Pumping Current)를 증가시켰다. 그리고 전하전달 트랜지스터의 게이트단에 프리차지회로 (Precharge Circuit)를 두어 대기모드진입 시 펌핑된 전하를 방전하지 못하고 고전압을 유지하여 소자의 신뢰성을 떨어트리는 문제를 해결하였다. 모의실험결과 펌핑전류, 펌핑효율(Pumping Efficiency), 파워효율(Power Efficiency) 모두 향상된 것을 확인하였고, $0.18{\mu}m$ Triple-Well 공정을 이용하여 Layout 하였다.

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UFIR 필터 Ladder 알고리즘 이용 GPS Holdover 성능 추정 (Estimation of GPS Holdover Performance with Ladder Algorithm Used for an UFIR Filter)

  • 이영규;양성훈;이창복;허문범
    • 제어로봇시스템학회논문지
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    • 제21권7호
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    • pp.669-676
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    • 2015
  • In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

냉온처리 전후의 광환경 조건이 오이 묘의 생존율에 미치는 영향 (Effect of Light Condition before and after Chilling Treatment on the Survival and Physiological Responses of Cucumber (Cucumis sativus L.) Seedlings)

  • Yooun Il Nam;Young Hoe Woo;Hyung Jun Kim
    • 생물환경조절학회지
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    • 제10권3호
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    • pp.165-171
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    • 2001
  • 겨울철 시설내에서 정전 등으로 인하여 수시간 동안 작물체가 생육한계 온도로 경과시 오이묘에 나타나는 피해와 피해발생의 생리적 요인 및 피해 경감대책을 구명하기 위하여 저온처리 전후의 광환경 조건이 오이 묘의 생존율 및 생육반응에 미치는 영향을 조사하였다. 냉온처리(2$^{\circ}C$, 48시간)에 따른 오이묘의 생존율은 암기말인 07:00시 처리에서 30.6%이었고, 암기 개시기인 18:00시 처리에서는 92.2%로 높았다. 세포의 전해질 누출은 07:00시 처리에서(72시간) 57.1%, 18:00시 처리에서는 25.9%로 낮았다. 누출액중 무기이온 함량은 $K^{+}$ 이온이 가장 많았고, $Na^{+}$, $Mg^{+2}$ , $Ca^{+2}$ 순으로 적었다. 냉온처리전 야간에 광을 조사하면 생존율이 광 무처리에 비해 56% 더 높아졌으며, 광조사는 2시간 처리로 충분한 효과가 있었다. 광 조사에 의하여 생존율이 높아지는 것은 광합성에 의한 당함량의 증가 때문인 것으로 해석 되었다. 냉온처리(3$^{\circ}C$, 48시간) 기간중 광을 조사하면, 생존율이 43.3%로 낮아진 반면, 암조건에두면 92%로 높았다.

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견관절 외상성 전방 불안정성에 대한 Bio-knotless 봉합 나사못을 이용한 관절경적 Bankart 병변 봉합술 (예비 보고) (Arthroscopic Bankart Repair in Traumatic Anterior Shoulder Instability with Bio-knotless Anchor (Preliminary and Technical Report))

  • 염재광;성기혁;신용운
    • Clinics in Shoulder and Elbow
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    • 제9권1호
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    • pp.105-110
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    • 2006
  • Purpose: This study reports the clinical results of the arthroscopic Bankart repair in traumatic anterior instability of the shoulder with bio-knotless anchor. Materials and Methods: 21 cases of 21 patients (20 male and 1 female) were included in this study. The average age was 24.8 years old and the period from the first injury to operation was average 37.2 months. All cases had Bankart lesion and 12 cases had Hill-Sachs' lesion. The SLAP lesion was associated in 6 cases. Preoperative Rowe score was average 29.1. Arthroscopic Bankart repair with bio-knotless anchor were performed in all cases; 3 anchors at 3, 4, 5 O'clock position of the glenoid were used in 11 cases and 2 anchors at 4, 5 O'clock position were used in 10 cases. All the associated SLAP lesions were repaired arthroscopically with bio-knotless anchor. Thermal capsular shrinkage at the anterior and inferior shoulder capsule after the Bankart repair was performed in 3 cases. The average follow up period was 20.2 months. Results: The Rowe score improved to 92.8, excellent in 17 cases and good in 4 cases, at last follow up period and 20 cases had full range of motion of the shoulder. 1 case had mild limited range of motion of the shoulder (150 degrees in flexion, 60 degrees in external rotation and T12 level in internal rotation) without any problem in normal activity. The arthroscopic revision surgery of the shoulder was performed in 1 case because of multiple traumatic injuries of the shoulder with pain postoperatively. Conclusion: Arthroscopic Bankart repair with bio-knotless anchor in traumatic anterior shoulder instability is one of the good methods because of the good clinical results.

Period3 유전자다형성과 기분 및 행동 계절성 변동의 연관성 (Association of the Period3 Gene Polymorphism and Seasonal Variations in Mood and Behavior)

  • 이헌정;강승걸;김린
    • 수면정신생리
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    • 제13권1호
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    • pp.22-26
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    • 2006
  • Circadian rhythms have been observed to be disturbed in mood disorders, especially seasonal affective disorder (SAD). Clock related gene variants also have been suggested to be associated with seasonality (seasonal variations in mood and behavior). This study tested the potential association between a length polymorphism of Period3 gene and seasonal variations in mood and behavior. 297 Korean college students were genotyped for the Period3 polymorphism and were for evaluated the seasonal variation by Seasonal Pattern Assessment Questionnaire (SPAQ). The genotype frequencies were 0.76 for 4R/4R, 0.22 for 4R/5R and 0.013 for 5R/5R. The global seasonality score was not different among Period3 gene variants (4R/4R, 4R/5R and 5R/5R) except for 'sleep length' subscore. The 5R/5R genotype showed the higher 'sleep length' subscore than others (p=0.024). The comparison between seasonals (syndromal plus subsyndromal SAD determined by SPAQ) and non-seasonals did not show any significant difference in frequencies of genotypes. These findings suggest that there is a possibility that the investigated Period3 polymorphism may play a partial role in the susceptibility of seasonal variations in a Korean population.

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FUZZY HYPERCUBES: A New Inference Machines

  • Kang, Hoon
    • 한국지능시스템학회논문지
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    • 제2권2호
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    • pp.34-41
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    • 1992
  • A robust and reliable learning and reasoning mechanism is addressed based upon fuzzy set theory and fuzzy associative memories. The mechanism stores a priori an initial knowledge base via approximate learning and utilizes this information for decision-making systems via fuzzy inferencing. We called this fuzzy computer architecture a 'fuzzy hypercube' processing all the rules in one clock period in parallel. Fuzzy hypercubes can be applied to control of a class of complex and highly nonlinear systems which suffer from vagueness uncertainty. Moreover, evidential aspects of a fuzzy hypercube are treated to assess the degree of certainty or reliability together with parameter sensitivity.

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TDX-1A의 디지틀 중계선 정합 프로세서의 성능분석 (The Performance Analysis of The Digital Trunk Circuit Processor in The TDX-1A)

  • 안지환;박광호;이용균
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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    • pp.510-513
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    • 1988
  • This paper describes an effective trunk loop signal processing method and analyzes execution time of program in the DTCP(Digital Trunk Circuit Processor) in the TDX-1A digital switching system. To predict a maximum trunk capacity, also analyzes to Z80A system clock(4Mbit/s, 2.5Mbit/s) and scanning period(8mS,5mS) respectively.

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VHDL 표현으로부터의 시간 지연 합성 (Timing Synthesis from VHDL Description)

  • 박상헌;최기영
    • 전자공학회논문지A
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    • 제31A권6호
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    • pp.209-221
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    • 1994
  • Timers are commonly used in hardware design for time delays that are to be much longer than the system clock period. In this paper, we present a method by which we can synthesie a hardware containing timers that implement long time delays described in VHDL. Because, in general, timers require high hardware cost, they must be utilized as efficiently as possible. To solve this problem we define a graph model and propose an algorithm that uses the graph model to minimize number of timers. A preliminary experimental result show that the algorithm implements all required time delays using minimum number of timers.

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고집적 메모리의 yield 개선을 위한 전기적 구제회로 (An Electrical Repair Circuit for Yield Increment of High Density Memory)

  • 김필중;김종빈
    • 한국전기전자재료학회논문지
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    • 제13권4호
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    • pp.273-279
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    • 2000
  • Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

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