• Title/Summary/Keyword: Clock Noise

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Algorithm for the Implementation of Network Interface Unit Transmitter in Broadband Wireless Local Loop (광대역 무선 가입자망(B-WLL)에서 가입자용 송신기 구현 알고리즘)

  • 최승남;황호선;김대진
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.41-44
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    • 1999
  • In this paper we proposed the algorithm for the implementation of network interface unit transmitter and analyzed its performance in broadband wireless local loop. The symbol rate of upstream transmitter is variable since the channel bandwidth of upstream can vary. Assuming that master clock ( $f_{DAC}$) is fixed, the cubic interpolator of Farrow structure is used to increase the sample rate to master clock rate. Simulation shows that the signal to noise ratio is about 54~55 dB and spurious signal power of upstream transmitter is less than 45 dB.B.

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Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

  • Na, Seung-in;Kim, Susie;Yang, Youngtae;Kim, Suhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.3
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    • pp.319-329
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    • 2016
  • High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

Ranging Performance Evaluation of Relative Frequency Offset Compensation in High Rate UWB (고속 UWB의 상대주파수 차이 보상에 의한 거리추정 성능평가)

  • Nam, Yoon-Suk;Lim, Jae-Geol;Jang, Ik-Hyeon
    • The Journal of the Korea Contents Association
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    • v.9 no.7
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    • pp.76-85
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    • 2009
  • UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area network. The node works on its local clock and the frequency differences of nodes have serious affects on ranging algorithms estimating locations of mobile nodes. The low rate UWB, IEEE802.15.4a, describes asynchronous two way ranging methods such as TWR and SDS-TWR working without any additional network synchronization, but the algorithms can not eliminate the effect of clock frequency differences. Therefore, the mechanisms to characterize the crystal difference is essential in typical UWB PHY implementations. In high rate UWB, characterizing of crystal offset with tracking loop is not required. But, detection of the clock frequency offset between the local clock and remote clock can be performed if there is little noise induced jitter. In this paper, we complete related ranging equations of high rate UWB based on TWR with relative frequency offset, and analyze a residual error in the ideal equations. We also evaluate the performance of the relative frequency offset algorithm by simulation and analyze the ranging errors according to the number of TWR to compensate coarse clock resolution. The results show that the relative frequency offset compensation and many times of TWR enhance the performance to converge to a limited ranging errors even with coarse clock resolutions.

Design of a PWM-Controlled Driving Device for Backlightsof LED Systems (LED 광원의 백 라이트에 대한 PWM 제어 및 구동 장치 설계)

  • Um, Kee-Hong
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.15 no.1
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    • pp.245-251
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    • 2015
  • In this paper, we present a design of PWM-controlled driving device for backlights in LED systems. The system can control either the brightness of the entire screen of backlights of LCD driven by LED or illumination or contrast of each partial segment of the entire screen. The PWM-controlled driving device includes the shift register that shifts the series data according to the clock signal prior to the generation of parallel data. It is also is comprised of a number of registers, a number of counters, a number of comparators, and a number of synchronizing gates (producing the PWM-controlled signals). The proposed device for backlights in LED systems can generate the PWM-controlled signal with a high degree of resolution without the increase of clock frequency. It also contains the PWM-controlled circuit that disperses and restrains the quantized noise.

Design and Fabrication of Clock Recovery Module for Gap Filter of Satellite DMB (위성 DMB 중계기용 클럭 재생 모듈 설계 및 제작)

  • Hong, Soon-Young;Shin, Yeoung-Seop;Hong, Sung-Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.4 s.119
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    • pp.423-429
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    • 2007
  • The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

Estimation of GPS Holdover Performance with Ladder Algorithm Used for an UFIR Filter (UFIR 필터 Ladder 알고리즘 이용 GPS Holdover 성능 추정)

  • Lee, Young-kyu;Yang, Sung-hoon;Lee, Chang-bok;Heo, Moon-beom
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.7
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    • pp.669-676
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    • 2015
  • In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

A compensation algorithm of cycle slip for synchronous stream cipher (동기식 스트림 암호 통신에 적합한 사이클 슬립 보상 알고리즘)

  • 윤장홍;강건우;황찬식
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.8
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    • pp.1765-1773
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    • 1997
  • The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.

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Development of Machine Learning Model to Predict Hydrogen Maser Holdover Time (수소 메이저 홀드오버 시간예측을 위한 머신러닝 모델 개발)

  • Sang Jun Kim;Young Kyu Lee;Joon Hyo Rhee;Juhyun Lee;Gyeong Won Choi;Ju-Ik Oh;Donghui Yu
    • Journal of Positioning, Navigation, and Timing
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    • v.13 no.1
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    • pp.111-115
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    • 2024
  • This study builds a machine learning model optimized for clocks among various techniques in the field of artificial intelligence and applies it to clock stabilization or synchronization technology based on atomic clock noise characteristics. In addition, the possibility of providing stable source clock data is confirmed through the characteristics of machine learning predicted values during holdover of atomic clocks. The proposed machine learning model is evaluated by comparing its performance with the AutoRegressive Integrated Moving Average (ARIMA) model, an existing statistical clock prediction model. From the results of the analysis, the prediction model proposed in this study (MSE: 9.47476) has a lower MSE value than the ARIMA model (MSE: 221.2622), which means that it provides more accurate predictions. The prediction accuracy is based on understanding the complex nature of data that changes over time and how well the model reflects this. The application of a machine learning prediction model can be seen as a way to overcome the limitations of the statistical-based ARIMA model in time series prediction and achieve improved prediction performance.

Hourly Environmental Pollution (Air Pollution and Noise) Mapping Method by the Traffic Volume Change (시간별 교통량 변화에 따른 환경오염지도(대기 및 소음) 구축방안에 관한 연구)

  • Cho, Dong-Myung;Kwon, Woo-Taeg;Na, Young
    • Journal of Environmental Impact Assessment
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    • v.16 no.6
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    • pp.485-494
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    • 2007
  • Air pollution and traffic noise from roads distributed near residential area has been a major social problem. In this study, an environmental pollution map for a residential area of Shihung-city was made by an expectation model based on hourly traffic volume change. Using the result from the model, a plan to reduce population in the residential area was established. The result of the modelling is summarized as follows: 1. At peak traffic hours (18 o'clock), 301-500 degree in hazardous and $d_{25}$ degree (25% of the residents are suffering extremely from the noise) in noise pollution were predicted in Jeongwang Main Road in Shihung city. 2. The calculated critical pollutant standard index, PSI showed the air pollution level, especially PM-10 high enough to require re-entrainment. 3. It was expected air pollution would extensively extend over the area distribution of each degree. However, noise pollution problem was limited to the area near roads.

Optimum Nonseparable Filter Bank Design in Multidimensional M-Band Subband Structure

  • Park, Kyu-Sik;Lee, Won-Cheol
    • The Journal of the Acoustical Society of Korea
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    • v.15 no.2E
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    • pp.24-32
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    • 1996
  • A rigorous theory for modeling, analysis, optimum nonseparable filter bank in multidimensional M-band quantized subband codec are developed in this paper. Each pdf-optimized quantizer is modeled by a nonlinear gain-plus-additive uncorrelated noise and embedded into the subband structure. We then decompose the analysis/synthesis filter banks into their polyphase components and shift the down-and up-samplers to the right and left of the analysis/synthesis polyphase matrices respectively. Focusing on the slow clock rate signal between the samplers, we derive the exact expression for the output mean square quantization error by using spatial-invariant analysis. We show that this error can be represented by two uncorrelated components : a distortion component due to the quantizer gain, and a random noise component due to fictitious uncorrelated noise at the uantizer. This mean square error is then minimized subject to perfect reconstruction (PR) constraints and the total bit allocation for the entire filter bank. The algorithm gives filter coefficients and subband bit allocations. Numerical design example for the optimum nonseparable orthonormal filter bank is given with a quincunx subsampling lattice.

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